公开(公告)号：US07143387B2

公开(公告)日：2006-11-28

申请号：US10651187

申请日：2003-08-28

申请人： James Stephen Fields, Jr. ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： James Stephen Fields, Jr. ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Methods, data processing systems, and program products are disclosed that support the definition and accessing of links indicating a relationship between configuration construct instances, such as Dial and Dial group instances, within a digital design. According to one method, first and second latches within the digital design are specified in at least one HDL statement within one or more HDL files representing the digital design. In the one or more HDL files, a first configuration construct instance referencing the first latch and a second configuration construct instance referencing the second latch are also defined. The first and second configuration construct instances provide interfaces through which values of the first and second latches can be accessed. In addition, a link indicating a relationship between the first and second configuration construct instances is also defined within the one or more HDL files.

摘要翻译： 公开了支持在数字设计中指示配置构造实例（例如拨号和拨号组实例）之间的关系的链接的定义和访问的方法，数据处理系统和程序产品。 根据一种方法，数字设计中的第一和第二锁存器在表示数字设计的一个或多个HDL文件内的至少一个HDL语句中被指定。 在一个或多个HDL文件中，还定义了引用第一锁存器的第一配置结构实例和引用第二锁存器的第二配置结构实例。 第一和第二配置构造实例提供可以访问第一和第二锁存器的值的接口。 此外，还在一个或多个HDL文件内定义指示第一和第二配置构造实例之间的关系的链接。

公开(公告)号：US07454577B2

公开(公告)日：2008-11-18

申请号：US11055476

申请日：2005-02-10

申请人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

发明人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F13/00

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

公开(公告)号：US08433851B2

公开(公告)日：2013-04-30

申请号：US11839663

申请日：2007-08-16

申请人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

发明人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0851 ,  G06F12/0864

摘要： A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

摘要翻译： 一种方法和计算机系统，用于通过重新配置扇区到片分配和较低的高速缓存寻址方案来减少具有扇区和分片的低级高速缓存的高速缓存子系统中的布线拥塞，所需的房地产和访问延迟。 通过这种分配，具有不连续地址的扇区被放置在相同的片内，并且基于对高速缓存片内的可寻址扇区的这种重新分配，可以在两级低级高速缓存之间进行简化布线方案。 此外，低速缓存有效地址标签被重新配置，使得先前分配用于识别扇区和片的地址字段相对于地址标签内的彼此的位置被切换。 地址位的这种重新分配使得能够基于指示的扇区进行直接片寻址。

公开(公告)号：US07480772B2

公开(公告)日：2009-01-20

申请号：US11835984

申请日：2007-08-08

申请人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

发明人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓存存储器和第二高速缓冲存储器，并且第二相干域包括远程一致高速缓存存储器。 第一高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 相关性状态字段具有多个可能的状态，包括指示存储器块可能与第一相关域中的第二高速缓冲存储器共享并且仅在第一相干域内缓存的状态。

公开(公告)号：US07774555B2

公开(公告)日：2010-08-10

申请号：US11835259

申请日：2007-08-07

申请人： James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Jeffrey Adam Stuecheli

发明人： James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Jeffrey Adam Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0813 ,  G06F12/0826

摘要： In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.

摘要翻译： 在包括至少第一和第二相干域的缓存相干数据处理系统中，存储器块与指示是否缓存存储器块的域指示符相关联地存储在系统存储器中，如果有的话，只有在第一一致性内 域。 第一相干域中的主设备通过参考存储在高速缓存中的域指示符来确定操作的广播传输的范围是否应超出第一相关域，然后在高速缓存相干数据处理中执行操作的广播 系统按照确定。

公开(公告)号：US06832342B2

公开(公告)日：2004-12-14

申请号：US09798289

申请日：2001-03-01

申请人： James Stephen Fields, Jr. ,  Michael Youhour Lim ,  Kevin F. Reick

发明人： James Stephen Fields, Jr. ,  Michael Youhour Lim ,  Kevin F. Reick

IPC分类号： G06F1100

CPC分类号： G06F11/0778 ,  G06F11/0712 ,  G06F11/0724

摘要： A method, apparatus, and computer implemented instructions for processing an error in a multiprocessor data processing system. An error is detected within the data processing system. A chip, causing the error, is identified within a plurality of chips to form an identified chip. Data is collected from the identified chip and hardware associated with the identified chip.

摘要翻译： 一种用于处理多处理器数据处理系统中的错误的方法，装置和计算机实现的指令。 在数据处理系统中检测到错误。 在多个芯片内识别导致错误的芯片，以形成识别的芯片。 从与识别的芯片相关联的所识别的芯片和硬件收集数据。

公开(公告)号：US06711652B2

公开(公告)日：2004-03-23

申请号：US09885999

申请日：2001-06-21

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr.

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr.

IPC分类号： G06F1200

CPC分类号： G06F12/0813

摘要： A non-uniform memory access (NUMA) computer system includes a remote node coupled by a node interconnect to a home node including a home system memory. The remote node includes a plurality of snoopers coupled to a local interconnect. The plurality of snoopers includes a cache that caches a cache line corresponding to but modified with respect to data resident in the home system memory. The cache has a cache controller that issues a deallocate operation on the local interconnect in response to deallocating the modified cache line. The remote node further includes a node controller, coupled between the local interconnect and the node interconnect, that transmits the deallocate operation to the home node with an indication of whether or not a copy of the cache line remains in the remote node following the deallocation. In this manner, the local memory directory associated with the home system memory can be updated to precisely reflect which nodes hold a copy of the cache line.

摘要翻译： 非均匀存储器访问（NUMA）计算机系统包括通过节点互连耦合到包括归属系统存储器的家庭节点的远程节点。 远程节点包括耦合到本地互连的多个窥探者。 多个窥探器包括高速缓存，其缓存对于相对于驻留在本地系统存储器中的数据而被修改的高速缓存线。 高速缓存具有缓存控制器，其响应于释放修改的高速缓存线而在本地互连上发出释放操作。 远程节点还包括耦合在本地互连和节点互连之间的节点控制器，其将取消分配操作发送到家庭节点，并指示在解除分配之后高速缓存行的副本是否保留在远程节点中。 以这种方式，可以更新与家庭系统存储器相关联的本地存储器目录，以精确地反映哪些节点保存高速缓存行的副本。

公开(公告)号：US06704843B1

公开(公告)日：2004-03-09

申请号：US09696890

申请日：2000-10-26

申请人： Ravi K. Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

发明人： Ravi K. Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

IPC分类号： G06F1208

CPC分类号： G06F12/0831

摘要： System bus snoopers within a multiprocessor system in which dynamic application sequence behavior information is maintained within cache directories append the dynamic application sequence behavior information for the target cache line to their snoop responses. The system controller, which may also maintain dynamic application sequence behavior information in a history directory, employs the available dynamic application sequence behavior information to append “hints” to the combined response, appends the concatenated dynamic application sequence behavior information to the combined response, or both. Either the hints or the dynamic application sequence behavior information may be employed by the bus master and other snoopers in cache management.

摘要翻译： 在多处理器系统内的系统总线监听器，其中动态应用程序行为信息保存在高速缓存目录中，将目标缓存行的动态应用程序序列行为信息附加到其监听响应。 也可以在历史目录中维护动态应用序列行为信息的系统控制器使用可用的动态应用序列行为信息来向组合响应附加“提示”，将连接的动态应用序列行为信息附加到组合响应，或 都。 在高速缓存管理中，总线主控和其他侦听器可以使用提示或动态应用序列行为信息。

公开(公告)号：US06678814B2

公开(公告)日：2004-01-13

申请号：US09895225

申请日：2001-06-29

申请人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

发明人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

IPC分类号： G06F1202

CPC分类号： G06F12/0223 ,  G06F9/5016

摘要： An apparatus for allocating data usage in an embedded dynamic random access memory (DRAM) device is disclosed. The apparatus for allocating data usages within an embedded dynamic random access memory (DRAM) device comprises a control analysis circuit, a data/command flow circuit, and a partition management control. The control analysis circuit generates an allocation signal in response to processing performances of a processor. Coupled to an embedded DRAM device, the data/command flow circuit controls data flow from the processor to the embedded DRAM device. The partition management control, coupled to the control analysis circuit, partitions the embedded DRAM device into a first partition and a second partition. The data stored in the first partition are different from the data stored in the second partition according to their respective usage. The allocation percentages of the first and second partitions are dynamically allocated by the allocation signal from the control analysis circuit.

摘要翻译： 公开了一种用于在嵌入式动态随机存取存储器（DRAM）装置中分配数据使用的装置。 用于在嵌入式动态随机存取存储器（DRAM）装置内分配数据用途的装置包括控制分析电路，数据/命令流电路和分区管理控制。 控制分析电路根据处理器的处理性能生成分配信号。 耦合到嵌入式DRAM设备，数据/命令流程电路控制从处理器到嵌入式DRAM设备的数据流。 耦合到控制分析电路的分区管理控制将嵌入式DRAM设备分割成第一分区和第二分区。 存储在第一分区中的数据根据​​它们各自的用途而不同于存储在第二分区中的数据。 通过来自控制分析电路的分配信号动态分配第一和第二分区的分配百分比。

公开(公告)号：US06671712B1

公开(公告)日：2003-12-30

申请号：US09436898

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

IPC分类号： G06F1516

CPC分类号： G06F13/4217

摘要： A data processing system includes a plurality of nodes, which each contain at least one agent, and data storage accessible to agents within the nodes. The plurality of nodes are coupled by a non-hierarchical interconnect including multiple non-blocking uni-directional address channels and at least one uni-directional data channel. The agents, which are each coupled to and snoop transactions on all of the plurality of address channels, can only issue transactions on an associated address channel. The uni-directional channels employed by the present non-hierarchical interconnect architecture permit high frequency pumped operation not possible with conventional bi-directional shared system buses. In addition, access latencies to remote (cache or main) memory incurred following local cache misses are greatly reduced as compared with conventional hierarchical systems because of the absence of inter-level (e.g., bus acquisition) communication latency. The non-hierarchical interconnect architecture also permits design flexibility in that the segment of the interconnect within each node can be independently implemented by a set of buses or as a switch, depending upon cost and performance considerations.

摘要翻译： 数据处理系统包括多个节点，每个节点包含至少一个代理，以及节点内的代理可访问的数据存储。 多个节点通过包括多个非阻塞单向地址信道和至少一个单向数据信道的非分层互连来耦合。 在所有多个地址信道上分别耦合到并且窥探事务的代理只能在相关联的地址信道上发布事务。 当前的非分层互连架构采用的单向信道允许高频抽运操作对于传统的双向共享系统总线是不可能的。 另外，与传统分层系统相比，由于没有层间（例如，总线采集）通信延迟，与本地高速缓存未命中所产生的远程（高速缓存或主）存储器的访问延迟大大降低。 非分层互连架构还允许设计灵活性，因为根据成本和性能考虑，每个节点内的互连部分可以由一组总线或开关单独地实现。