-
71.发明授权Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains 有权量子阱MOSFET通道由金属源/漏极引起的单轴应变，以及保形再生长源/漏极公开(公告)号：US08258498B2
公开(公告)日：2012-09-04
申请号：US13017862
申请日：2011-01-31
申请人： Prashant Majhi , Mantu Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
发明人： Prashant Majhi , Mantu Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
IPC分类号： H01L29/06 , H01L31/072 , H01L31/0336 , H01L31/0328 , H01L31/109
CPC分类号： H01L29/66431 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76897 , H01L29/152 , H01L29/165 , H01L29/41766 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7848 , H01L29/802
摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
摘要翻译： 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。
-
72.发明申请Carrier mobility in surface-channel transistors, apparatus made therewith, and systems containing same 有权表面沟道晶体管中的载流子迁移率，由其制成的装置以及包含该载流子迁移率的系统公开(公告)号：US20100289062A1
公开(公告)日：2010-11-18
申请号：US12454354
申请日：2009-05-15
IPC分类号： H01L29/20
CPC分类号： H01L29/66522 , H01L29/1054 , H01L29/122 , H01L29/205 , H01L29/66477
摘要： A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers.
摘要翻译： 表面沟道晶体管设置在半导体器件中。 表面沟道晶体管是PMOS或NMOS器件。 外延层设置在表面沟道晶体管的上方，导致更接近器件表面的带隙现象增加。 形成表面沟道晶体管的工艺包括对外延层进行分级。
-
公开(公告)号：US20100163926A1
公开(公告)日：2010-07-01
申请号：US12345489
申请日：2008-12-29
IPC分类号： H01L29/267 , H01L21/336
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/66795
摘要： Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.
摘要翻译： 通常描述调制掺杂多栅极器件。 在一个示例中，设备包括具有表面的半导体衬底，耦合到半导体衬底的表面的一个或多个缓冲膜，耦合到该一个或多个缓冲膜的第一阻挡膜，耦合到第一 所述多栅极鳍片包括源极区域，漏极区域和多栅极器件的沟道区域，其中所述沟道区域设置在所述源极区域和所述漏极区域之间，间隔膜耦合到所述多栅极器件， 栅极鳍片以及耦合到间隔膜的掺杂膜。
-
74.发明授权Method of forming quantum well mosfet channels having uni-axial strains caused by metal source/drains 有权形成具有由金属源/排水管引起的单轴应变的量子阱mosfet通道的方法公开(公告)号：US08501508B2
公开(公告)日：2013-08-06
申请号：US13479121
申请日：2012-05-23
申请人： Prashant Majhi , Mantu Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
发明人： Prashant Majhi , Mantu Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
IPC分类号： H01L21/00
CPC分类号： H01L29/66431 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76897 , H01L29/152 , H01L29/165 , H01L29/41766 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7848 , H01L29/802
摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
摘要翻译： 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。
-
公开(公告)号：US08120063B2
公开(公告)日：2012-02-21
申请号：US12345489
申请日：2008-12-29
IPC分类号： H01L29/267
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/66795
摘要： Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.
摘要翻译： 通常描述调制掺杂多栅极器件。 在一个示例中，设备包括具有表面的半导体衬底，耦合到半导体衬底的表面的一个或多个缓冲膜，耦合到该一个或多个缓冲膜的第一阻挡膜，耦合到第一 所述多栅极鳍片包括源极区域，漏极区域和多栅极器件的沟道区域，其中所述沟道区域设置在所述源极区域和所述漏极区域之间，间隔膜耦合到所述多栅极器件， 栅极鳍片以及耦合到间隔膜的掺杂膜。
-
公开(公告)号：US20120018781A1
公开(公告)日：2012-01-26
申请号：US13248197
申请日：2011-09-29
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/66795
摘要： Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.
摘要翻译： 通常描述调制掺杂多栅极器件。 在一个示例中，设备包括具有表面的半导体衬底，耦合到半导体衬底的表面的一个或多个缓冲膜，耦合到该一个或多个缓冲膜的第一阻挡膜，耦合到第一 所述多栅极鳍片包括源极区域，漏极区域和多栅极器件的沟道区域，其中所述沟道区域设置在所述源极区域和所述漏极区域之间，间隔膜耦合到所述多栅极器件， 栅极鳍片以及耦合到间隔膜的掺杂膜。
-
77.发明申请QUANTUM WELL MOSFET CHANNELS HAVING UNI-AXIAL STRAIN CAUSED BY METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS 有权具有由金属源/排水源引起的不均匀应变的QUANTUM WELL MOSFET通道，以及合适的反应源/漏极公开(公告)号：US20100193771A1
公开(公告)日：2010-08-05
申请号：US12756989
申请日：2010-04-08
申请人： Prashant Majhi , Mantu K. Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
发明人： Prashant Majhi , Mantu K. Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
IPC分类号： H01L29/772
CPC分类号： H01L29/66431 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76897 , H01L29/152 , H01L29/165 , H01L29/41766 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7848 , H01L29/802
摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
摘要翻译： 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。
-
公开(公告)号：US20100163847A1
公开(公告)日：2010-07-01
申请号：US12347268
申请日：2008-12-31
申请人： Prashant Majhi , Mantu K. Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
发明人： Prashant Majhi , Mantu K. Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
IPC分类号： H01L29/12 , H01L21/336 , H01L21/18 , H01L21/203
CPC分类号： H01L29/66431 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76897 , H01L29/152 , H01L29/165 , H01L29/41766 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7848 , H01L29/802
摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
-
79.发明授权Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains 有权量子阱MOSFET通道由金属源/漏极引起的单轴应变，以及保形再生长源/漏极公开(公告)号：US07947971B2
公开(公告)日：2011-05-24
申请号：US12756989
申请日：2010-04-08
申请人： Prashant Majhi , Mantu Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
发明人： Prashant Majhi , Mantu Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
IPC分类号： H01L29/06 , H01L31/072 , H01L31/0336 , H01L31/0328 , H01L31/109
CPC分类号： H01L29/66431 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76897 , H01L29/152 , H01L29/165 , H01L29/41766 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7848 , H01L29/802
摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
摘要翻译： 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。
-
公开(公告)号：US10290614B2
公开(公告)日：2019-05-14
申请号：US13977195
申请日：2011-12-19
申请人： Han Wui Then , Robert Chau , Valluri Rao , Niloy Mukherjee , Marko Radosavljevic , Ravi Pillarisetty , Gilbert Dewey , Jack Kavalieros
发明人： Han Wui Then , Robert Chau , Valluri Rao , Niloy Mukherjee , Marko Radosavljevic , Ravi Pillarisetty , Gilbert Dewey , Jack Kavalieros
IPC分类号： H01L25/00 , H01L25/07 , H01L27/06 , H01L29/20 , H01L29/66 , H01L29/78 , H01L27/088 , H01L29/423 , H01L29/778 , H01L21/8252 , H01L21/8258
摘要： System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.
-
-
-
-
-
-
-
-
-
搜索结果
196 条记录 (耗时 0.045 秒)
