公开(公告)号：US20220146872A1

公开(公告)日：2022-05-12

申请号：US17582167

申请日：2022-01-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki ,  Hiroyuki Miyake

IPC: G02F1/1368 ,  G02F1/1362

Abstract: An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.

公开(公告)号：US11295649B2

公开(公告)日：2022-04-05

申请号：US16784383

申请日：2020-02-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  H03K19/01 ,  H01L27/12 ,  G09G3/20 ,  H03K3/356 ,  G11C19/18 ,  G11C19/28 ,  H03K19/0185 ,  H03K17/06 ,  H03K17/081 ,  G02F1/167 ,  G02F1/1368 ,  G09G3/3225 ,  G09G3/34 ,  H01L27/32 ,  H01L29/786

Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

公开(公告)号：US20220091467A1

公开(公告)日：2022-03-24

申请号：US17541423

申请日：2021-12-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G02F1/1362 ,  G09G3/34 ,  G09G3/36 ,  G11C19/28 ,  H01L27/06 ,  H01L27/15 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  G02F1/133 ,  G02F1/1345 ,  G02F1/1368

Abstract: A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.

公开(公告)号：US20220005835A1

公开(公告)日：2022-01-06

申请号：US17476748

申请日：2021-09-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H01L27/12 ,  G09G3/20 ,  G09G3/325 ,  G09G3/36 ,  G11C19/28 ,  H03K3/356 ,  H03K19/003 ,  G02F1/1362

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

公开(公告)号：US11133335B2

公开(公告)日：2021-09-28

申请号：US16440528

申请日：2019-06-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/28 ,  H01L27/12 ,  G02F1/1362 ,  G09G3/20 ,  G09G3/325 ,  G09G3/36 ,  H03K19/003 ,  H03K3/356 ,  G09G3/3266 ,  G09G3/3258

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

公开(公告)号：US20210272644A1

公开(公告)日：2021-09-02

申请号：US17325374

申请日：2021-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/28 ,  H01L27/088 ,  H01L27/12 ,  G09G3/20 ,  H01L27/15 ,  H01L29/786

Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

公开(公告)号：US11017871B2

公开(公告)日：2021-05-25

申请号：US17016635

申请日：2020-09-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/00 ,  G11C19/28 ,  H01L27/088 ,  H01L27/12 ,  G09G3/20 ,  H01L29/786 ,  H01L27/15 ,  G09G3/36 ,  H01L27/32

Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

公开(公告)号：US10971103B2

公开(公告)日：2021-04-06

申请号：US16812604

申请日：2020-03-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  G11C19/28 ,  G11C19/18 ,  H01L27/12

Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

公开(公告)号：US10896633B2

公开(公告)日：2021-01-19

申请号：US15594792

申请日：2017-05-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki

IPC: G09G3/14 ,  G11C19/28 ,  G09G3/36 ,  G02F1/133 ,  G06F3/038 ,  G09G3/20

Abstract: To suppress degradation of a transistor. A method for driving a liquid crystal display device has a first period and a second period. In the first period, a first transistor and a second transistor are alternately turned on and off repeatedly, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are alternately turned on and off repeatedly. Accordingly, the time during which the transistor is on can be reduced, so that degradation of characteristics of the transistor can be suppressed.

公开(公告)号：US10854641B2

公开(公告)日：2020-12-01

申请号：US16823785

申请日：2020-03-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki ,  Shunpei Yamazaki

IPC: H01L29/12 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1333 ,  G02F1/1334 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/20 ,  G09G3/36 ,  H01L29/24 ,  H01L21/8234

Abstract: An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less.