公开(公告)号：US20230238437A1

公开(公告)日：2023-07-27

申请号：US18194490

申请日：2023-03-31

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L29/417 ,  H01L29/10

CPC分类号： H01L29/41741 ,  H01L29/1037

摘要： A semiconductor device includes a stacked structure with first conductive layers and insulating layers that are stacked alternately with each other, second conductive layers located on the stacked structure, first openings passing through the second conductive layers and the stacked structure and having a first width, second conductive patterns formed in the first openings and located on the stacked structure to be electrically coupled to the second conductive layers, data storage patterns formed in the first openings and located under the second conductive patterns, and channel layers formed in the data storage patterns and the second conductive patterns.

公开(公告)号：US20230058892A1

公开(公告)日：2023-02-23

申请号：US17982056

申请日：2022-11-07

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/1158 ,  H01L27/1157 ,  H01L27/11582

摘要： A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other, and a channel structure passing through the stack structure and the etch prevention layer, wherein a lower portion of the channel structure is located in the source structure and a sidewall of the lower portion of the channel structure is in direct contact with the source structure.

公开(公告)号：US20220415910A1

公开(公告)日：2022-12-29

申请号：US17900429

申请日：2022-08-31

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/1158 ,  H01L27/1157 ,  H01L27/11582

摘要： A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other, and a channel structure passing through the stack structure and the etch prevention layer, wherein a lower portion of the channel structure is located in the source structure and a sidewall of the lower portion of the channel structure is in direct contact with the source structure.

公开(公告)号：US20220189980A1

公开(公告)日：2022-06-16

申请号：US17353408

申请日：2021-06-21

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/11551 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11578 ,  H01L27/11565

摘要： A semiconductor device includes: conductive layers and interlayer insulating layers, which are alternately stacked; a select conductor spaced apart from the conductive layers; cell plugs penetrating the conductive layers, the interlayer insulating layers, and the select conductor; and an auxiliary conductor in contact with the select conductor.

公开(公告)号：US20220093635A1

公开(公告)日：2022-03-24

申请号：US17189926

申请日：2021-03-02

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/528

摘要： There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate conductive pattern including a first horizontal part and a second horizontal part and a third horizontal part connected to one end portion of the first horizontal part; a first insulating pattern disposed between the first horizontal part and the second horizontal part of the first gate conductive pattern; and a second gate conductive pattern including a first horizontal part and a second horizontal part and a third horizontal part connected to one end portion of the second horizontal part of the second gate conductive pattern; a first gate contact structure extending vertically on a contact region, the first gate contact structure being in contact with the first gate conductive pattern while penetrating the third horizontal part of the first gate conductive pattern.

公开(公告)号：US20220068962A1

公开(公告)日：2022-03-03

申请号：US17192262

申请日：2021-03-04

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/11582 ,  H01L23/522 ,  H01L27/11556

摘要： There are provided a semiconductor memory device and a manufacturing method of the semiconductor including: a plurality of source channels penetrating a source select line; a gate stack structure overlapping with the source select line; a connection pattern disposed between the source select line and the gate stack structure, the connection pattern being commonly connected to the plurality of source channels; and a plurality of vertical channels penetrating the gate stack structure, the plurality of vertical channels being commonly connected to the connection pattern.

公开(公告)号：US20220037501A1

公开(公告)日：2022-02-03

申请号：US17161080

申请日：2021-01-28

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L29/45 ,  H01L29/78

摘要： The present technology provides a semiconductor device. The semiconductor device includes a stack including insulating patterns and conductive patterns stacked alternately with each other, a channel layer including a first channel portion protruding out of the stack and a second channel portion in the stack, and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion includes metal silicide.

公开(公告)号：US20220028778A1

公开(公告)日：2022-01-27

申请号：US17158860

申请日：2021-01-26

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L23/528 ,  H01L27/11582

摘要： A semiconductor device includes: a stack structure including conductive patterns and stack insulating layers, which are alternately stacked; a channel structure penetrating the stack structure; a tunnel insulating layer surrounding the channel structure; a cell storage pattern surrounding the tunnel insulating layer; and a dummy storage pattern surrounding the tunnel insulating layer, the dummy storage pattern being spaced apart from the cell storage pattern. The conductive patterns include a select conductive pattern in contact with the tunnel insulating layer.

公开(公告)号：US20210407585A1

公开(公告)日：2021-12-30

申请号：US17473648

申请日：2021-09-13

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： G11C11/413 ,  H01L27/11

摘要： There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.

公开(公告)号：US20210327805A1

公开(公告)日：2021-10-21

申请号：US17030013

申请日：2020-09-23

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L23/522 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/14 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/768

摘要： There are provided a semiconductor memory device and an erasing method of the semiconductor memory device. The semiconductor memory device includes: a plurality of word lines stacked between a source conductive pattern and a bit line; at least two drain select lines disposed between the plurality word lines and the bit line, the at least two drain select lines being spaced apart from each other in an extending direction of the bit line; and an erase control line disposed between the at least two drain select lines and the plurality of word lines.