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公开(公告)号:US20190165170A1
公开(公告)日:2019-05-30
申请号:US16264384
申请日:2019-01-31
发明人: Marco SAMBI , Fabrizio Fausto Renzo TOIA , Marco MARCHESI , Marco MORELLI , Riccardo DEPETRO , Giuseppe BARILLARO , Lucanos Marsilio STRAMBINI
IPC分类号: H01L29/78 , H01L21/02 , H01L29/66 , H01L29/06 , H01L29/36 , H01L29/08 , H01L29/16 , H01L21/308 , H01L29/32 , H03K17/687 , H01L29/417 , H01L21/265 , H01L29/861 , H01L21/762 , H01L21/3063
CPC分类号: H01L29/7827 , H01L21/02233 , H01L21/02255 , H01L21/26513 , H01L21/3063 , H01L21/3081 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0665 , H01L29/0847 , H01L29/16 , H01L29/32 , H01L29/36 , H01L29/41741 , H01L29/66128 , H01L29/66666 , H01L29/66681 , H01L29/7816 , H01L29/8611 , H03K17/687
摘要: A process of forming integrated electronic device having a semiconductor body includes: forming a first electrode region having a first type of conductivity; forming a second electrode region having a second type of conductivity, which forms a junction with the first electrode region; and forming a nanostructured semiconductor region, which extends in one of the first and second electrode regions.
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公开(公告)号:US20190165166A1
公开(公告)日:2019-05-30
申请号:US16263643
申请日:2019-01-31
IPC分类号: H01L29/78 , H01L29/16 , H01L29/423 , H01L29/417 , H01L29/36 , H01L29/10 , H01L29/08 , H01L29/06 , H01L21/04 , H01L29/66 , H01L29/12 , H01L21/02
CPC分类号: H01L29/7813 , H01L21/02378 , H01L21/02529 , H01L21/02634 , H01L21/0274 , H01L21/0465 , H01L21/0475 , H01L21/0485 , H01L21/049 , H01L29/06 , H01L29/0623 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/12 , H01L29/1608 , H01L29/167 , H01L29/36 , H01L29/41741 , H01L29/4236 , H01L29/45 , H01L29/66068 , H01L29/66734 , H01L29/78
摘要: In a first main surface side of a silicon carbide semiconductor base, a trench is formed. A second base region of a second conductivity type is arranged at a position facing the trench in a depth direction. An end (toward a drain electrode) of the second base region of the second conductivity type, and an end (toward the drain electrode) of a first base region of the second conductivity type reach a position deeper than an end (toward the drain electrode) of a region of a first conductivity type. Thus, the electric field at a gate insulating film at the trench bottom is mitigated, suppressing the breakdown voltage of the active region and enabling breakdown voltage design of the edge termination region to be facilitated. Further, such a semiconductor device may be formed by an easy method of manufacturing.
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3.
公开(公告)号:US20190140047A1
公开(公告)日:2019-05-09
申请号:US16181051
申请日:2018-11-05
IPC分类号: H01L29/06 , H01L29/16 , H01L29/417 , H01L29/66 , H01L29/78
CPC分类号: H01L29/0626 , H01L29/1095 , H01L29/1608 , H01L29/41741 , H01L29/66712 , H01L29/66719 , H01L29/7802
摘要: A power transistor assembly and method of mitigating short channel effects in a power transistor assembly are provided. The power transistor assembly includes a first layer of semiconductor material formed of a first conductivity type material and a hard mask layer covering at least a portion of the first layer and having a window therethrough exposing a surface of the first layer. The power transistor assembly also includes a first region formed in the first layer of semiconductor material of a second conductivity type material and aligned with the window, one or more source regions formed of first conductivity type material within the first region and separated by a portion of the first region, and an extension of the first region extending laterally through the surface of the first layer.
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公开(公告)号:US20190058060A1
公开(公告)日:2019-02-21
申请号:US16075840
申请日:2016-12-26
发明人: Jun SAITO , Sachiko AOI , Yasushi URAKAMI
IPC分类号: H01L29/78 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/16 , H01L29/36 , H01L21/04 , H01L21/265 , H01L29/06 , H01L29/66
CPC分类号: H01L29/7813 , H01L21/047 , H01L21/26513 , H01L21/26586 , H01L29/0623 , H01L29/0696 , H01L29/0865 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/36 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/66068 , H01L29/66348 , H01L29/66734 , H01L29/7397
摘要: A trench gate semiconductor switching element is provided. The semiconductor substrate of the element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench, and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region. The bottom region includes a first bottom region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench and extending from the bottom surface to a first position; and a second bottom region in contact with the gate insulation layer in a second range adjacent to the first range and extending from the bottom surface to a second position lower than the first position.
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5.
公开(公告)号:US20190013385A1
公开(公告)日:2019-01-10
申请号:US15902116
申请日:2018-02-22
IPC分类号: H01L29/417 , H01L29/78 , H01L29/16 , H01L29/10 , H01L29/06
CPC分类号: H01L29/41741 , H01L29/0623 , H01L29/0696 , H01L29/1087 , H01L29/1608 , H01L29/41766 , H01L29/66068 , H01L29/7805 , H01L29/7813
摘要: A gate trench and a protective trench are provided on a top surface of the silicon carbide semiconductor layer of a first conductivity type. A protective diffusion layer of a second conductivity type is provided at a position deeper than the gate electrode in the silicon carbide semiconductor layer. An inter-layer insulating film covers a surface of the gate electrode and includes a cell opening. A source electrode is electrically connected to the source region via the cell opening and electrically connected to the protective diffusion layer via the protective trench. A plated film is provided on the source electrode. A concave part is provided on a top surface of the source electrode above the protective trench. A depth in a vertical direction of the concave part is equal to or less than half of a width in a horizontal direction of the concave part.
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公开(公告)号:US20180358445A1
公开(公告)日:2018-12-13
申请号:US15993671
申请日:2018-05-31
发明人: Yusuke Kobayashi , Naoyuki Ohse , Shinsuke Harada
CPC分类号: H01L29/41741 , H01L29/063 , H01L29/1095 , H01L29/1608 , H01L29/45 , H01L29/7813
摘要: At a front surface of a silicon carbide base, an n−-type drift layer, a p-type base layer, a first n+-type source region, a second n+-type source region, and a trench that penetrates the first and the second n+-type source regions and the p-type base layer and reaches the n-type region are provided. In the trench, the gate electrode is provided via a gate insulating film, an interlayer insulating film is provided on the gate electrode, and a barrier metal is provided on the interlayer insulating film.
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7.
公开(公告)号:US20180350761A1
公开(公告)日:2018-12-06
申请号:US16101114
申请日:2018-08-10
IPC分类号: H01L23/00 , H01L21/768 , H01L23/532 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/66 , H01L29/739
CPC分类号: H01L24/05 , H01L21/76843 , H01L21/76858 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L24/03 , H01L29/407 , H01L29/417 , H01L29/41741 , H01L29/42376 , H01L29/45 , H01L29/6634 , H01L29/66348 , H01L29/7396 , H01L29/7397 , H01L2224/0345 , H01L2224/03462 , H01L2224/03848 , H01L2224/03912 , H01L2224/05022 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05572 , H01L2224/05582 , H01L2224/05583 , H01L2224/05611 , H01L2224/05616 , H01L2224/05618 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2924/13055 , H01L2924/13091 , H01L2924/3512 , H01L2924/00014 , H01L2924/01029 , H01L2924/01013 , H01L2924/01074
摘要: A method of manufacturing a semiconductor device includes forming a semiconductor substrate that has a conductive structure, and forming a precursor auxiliary layer stack on a first section of the conductive structure. The precursor auxiliary layer stack has a precursor adhesion layer and a precursor barrier layer between the precursor adhesion layer and the conductive structure. The precursor adhesion layer contains a second metal. The method further includes forming, on the precursor auxiliary layer stack, a metal structure containing a first metal and forming, from portions of the precursor auxiliary layer stack an adhesive layer containing the first and second metals.
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公开(公告)号:US20180342592A1
公开(公告)日:2018-11-29
申请号:US16037698
申请日:2018-07-17
发明人: Kangguo Cheng , Ruilong Xie , Tenko Yamashita , Chun-Chen Yeh
IPC分类号: H01L29/417 , H01L29/78 , H01L21/28 , H01L29/66 , H01L21/3065 , H01L21/308 , H01L29/786 , H01L21/02 , H01L29/49 , H01L29/423 , H01L29/51
CPC分类号: H01L29/41741 , H01L21/02266 , H01L21/28114 , H01L21/28123 , H01L21/3065 , H01L21/308 , H01L29/42392 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66666 , H01L29/66787 , H01L29/7827 , H01L29/78618 , H01L29/78642 , H01L29/78696
摘要: A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.
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公开(公告)号:US20180342524A1
公开(公告)日:2018-11-29
申请号:US15980604
申请日:2018-05-15
申请人: IMEC VZW
发明人: Julien Ryckaert , Naoto Horiguchi , Dan Mocuta , Trong Huynh Bao
IPC分类号: H01L27/11 , H01L27/092 , H01L29/15 , H01L29/66 , H01L29/78
CPC分类号: H01L27/1104 , H01L21/823431 , H01L21/823487 , H01L21/823885 , H01L27/0886 , H01L27/092 , H01L29/41741 , H01L29/66666 , H01L29/66787 , H01L29/7827 , H01L29/785 , H01L29/78642 , H01L2029/7858
摘要: The disclosed technology generally relates semiconductor devices and more particularly to a vertical transistor device, and a method of fabricating the same. In one aspect, the method includes providing, on a substrate, a fin formed of a stack of a first layer, a second layer and a third layer, wherein the second layer is positioned above the first layer and the third layer is positioned above the second layer. The method additionally includes forming a dielectric on the sidewalls of the first and third layers of the fin selectively against a sidewall of the second layer, and the method additionally includes forming a gate contacting layer for contacting a sidewall of the second layer. The first and third layers define a source region and a drain region, respectively, of the vertical transistor device. The second layer defines a channel region of the vertical transistor device. The dielectric on the sidewalls of the first and third layers electrically isolates the source and drain regions from the gate contacting layer.
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公开(公告)号:US20180337059A1
公开(公告)日:2018-11-22
申请号:US16034828
申请日:2018-07-13
IPC分类号: H01L21/308 , H01L29/417 , H01L21/306 , H01L29/78 , H01L29/66 , H01L29/423 , H01L21/28 , H01L29/10 , H01L29/08 , H01L29/06 , H01L27/12 , H01L23/535 , H01L21/768 , H01L29/786
CPC分类号: H01L21/3085 , H01L21/28008 , H01L21/30604 , H01L21/76895 , H01L23/535 , H01L27/1207 , H01L29/0649 , H01L29/0847 , H01L29/1037 , H01L29/41741 , H01L29/4236 , H01L29/42392 , H01L29/66553 , H01L29/66666 , H01L29/7827 , H01L29/783 , H01L29/78615 , H01L29/78642
摘要: A method of forming a substrate contact in a vertical transistor device includes patterning a sacrificial layer to form an opening in the sacrificial layer, the sacrificial layer disposed on hardmask arranged on a substrate, and the substrate including a bulk semiconductor layer, a buried oxide layer arranged on the bulk semiconductor layer, and a semiconductor layer arranged on the buried oxide layer; forming oxide spacers on sidewalls of the opening in the sacrificial layer; using the oxide spacers as a pattern to etch a trench through the substrate, the trench stopping at a region within the bulk semiconductor layer; and depositing a conductive material in the trench to form the substrate contact.
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