公开(公告)号：US20200006387A1

公开(公告)日：2020-01-02

申请号：US16453976

申请日：2019-06-26

Applicant: Samsung Display Co., Ltd.

Inventor： Yeon Keon MOON ,  Kano MASATAKA ,  Myoung Hwa KIM ,  Jun Hyung LIM

IPC: H01L27/12 ,  H01L29/786 ,  G09G3/36

Abstract: A display device in which a display area and a non-display area are defined, the display device including a wiring substrate, the wiring substrate including: a base substrate; a first thin film transistor disposed on the base substrate, located in the non-display area, and including a first gate pattern, a first semiconductor pattern disposed on the first gate pattern, a first source pattern disposed on the first semiconductor pattern, and a first drain pattern disposed on the first semiconductor pattern and spaced apart from the first source pattern; and a second thin film transistor disposed on the base substrate and located in the display area. A first channel width of the first thin film transistor is greater than a first overlap length of the first gate pattern, the first semiconductor pattern, and the first drain pattern.

公开(公告)号：US20160155753A1

公开(公告)日：2016-06-02

申请号：US14664589

申请日：2015-03-20

Applicant: Samsung Display Co. Ltd.

Inventor： MASATAKA KANO ,  Yeon Keon MOON ,  Jung Hun NOH ,  Jun Hyung LIM ,  So Young KOO ,  Myoung Hwa KIM

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1222 ,  H01L27/1225

Abstract: The display device includes a substrate, a first gate line extending in a first direction on the substrate, a gate insulating layer formed on the substrate to cover the first gate line, a first semiconductor pattern formed on the gate insulating layer to overlap the first gate line, and including a first region and a second region, a first data line extending in a second direction that is crossing the first gate line on the gate insulating layer, and including a source electrode region that overlaps the first region of the first semiconductor pattern, a drain electrode spaced apart from the source electrode region and formed on the second region of the first semiconductor pattern, and a pixel electrode formed on the drain electrode and electrically connected to the drain electrode. The first semiconductor pattern is arranged in a third direction between the first direction and the second direction.

Abstract translation: 显示装置包括基板，在基板上沿第一方向延伸的第一栅极线，形成在基板上以覆盖第一栅极线的栅极绝缘层，形成在栅极绝缘层上以与第一栅极重叠的第一半导体图案 并且包括第一区域和第二区域，在与栅极绝缘层上的第一栅极线交叉的第二方向上延伸的第一数据线，并且包括与第一半导体图案的第一区域重叠的源极区域 与源电极区间隔开并形成在第一半导体图案的第二区上的漏电极，以及形成在漏电极上并电连接到漏电极的像素电极。 第一半导体图案在第一方向和第二方向之间沿第三方向排列。

公开(公告)号：US20140291665A1

公开(公告)日：2014-10-02

申请号：US14180171

申请日：2014-02-13

Applicant: Samsung Display Co., Ltd.

Inventor： Gun Hee KIM ,  Jin Hyun PARK ,  Kyoung Won LEE ,  Byung Du AHN ,  Jee-Hun LIM ,  Jun Hyung LIM

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1288

Abstract: A thin film transistor array panel includes: a gate electrode disposed on a substrate, an insulating layer disposed on the gate electrode, an oxide semiconductor disposed on the gate insulating layer, source electrode overlapping a portion of the oxide semiconductor, a drain electrode overlapping another portion of the oxide semiconductor; and a buffer layer disposed between the oxide semiconductor and the source electrode and between the oxide semiconductor and the drain electrode. The buffer layer comprises tin as a doping material. A weight percent of the doping material is greater than approximately 0% and less than or equal to approximately 20%.

Abstract translation: 薄膜晶体管阵列面板包括：设置在基板上的栅极电极，设置在栅电极上的绝缘层，设置在栅极绝缘层上的氧化物半导体，与氧化物半导体的一部分重叠的源电极，与另一个重叠的漏电极 部分氧化物半导体; 以及设置在氧化物半导体和源电极之间以及氧化物半导体和漏电极之间的缓冲层。 缓冲层包含锡作为掺杂材料。 掺杂材料的重量百分比大于约0％且小于或等于约20％。

公开(公告)号：US20130306965A1

公开(公告)日：2013-11-21

申请号：US13664180

申请日：2012-10-30

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Du AHN ,  Jun Hyung LIM ,  Jin Seong PARK

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78693

Abstract: A thin film transistor includes: a gate electrode on a substrate; a source electrode; a drain electrode positioned in a same layer as the source electrode and facing the source electrode; an oxide semiconductor layer positioned between the gate electrode and the source electrode or drain electrode; and a gate insulating layer positioned between the gate electrode and the source electrode or drain electrode. The oxide semiconductor layer includes titanium oxide (TiOx) doped with niobium (Nb).

Abstract translation: 薄膜晶体管包括：衬底上的栅电极; 源电极; 位于与源电极相同的层并且面对源电极的漏电极; 位于所述栅电极和所述源电极或漏电极之间的氧化物半导体层; 以及位于栅电极和源电极或漏电极之间的栅极绝缘层。 氧化物半导体层包括掺杂有铌（Nb）的氧化钛（TiOx）。