-
公开(公告)号：US20220326368A1
公开(公告)日：2022-10-13
申请号：US17843069
申请日：2022-06-17
Applicant: Texas Instruments Incorporated
Inventor： Sandeep Rao , Karthik Subburaj , Sriram Murali , Karthik Ramasubramanian
IPC: G01S13/28 , G06F17/14 , G01S7/41 , G01S13/536 , G01S13/931 , G01S13/34 , G01S7/35
Abstract: A radar system is provided that includes a radar transceiver integrated circuit (IC) configurable to transmit a first frame of chirps, and another radar transceiver IC configurable to transmit a second frame of chirps at a time delay ΔT, wherein ΔT=Tc/K, K≥2 and Tc is an elapsed time from a start of one chirp in the first frame and the second frame and a start of a next chirp in the first frame and the second frame, wherein the radar system is configured to determine a velocity of an object in a field of view of the radar system based on first digital intermediate frequency signals generated responsive to receiving reflected chirps of the first frame and second digital IF signals generated responsive to receiving reflected chirps of the time delayed second frame, wherein the maximum measurable velocity is increased by a factor of K.
-
公开(公告)号：US20220196824A1
公开(公告)日：2022-06-23
申请号：US17132857
申请日：2020-12-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sandeep Rao , Karthik Subburaj
Abstract: A radar system is provided and includes a radar transceiver integrated circuit (IC) and a processor coupled to the radar transceiver IC. The radar transceiver IC includes a chirp generator configured to generate a plurality of chirp signals and a phase shifter configured to induce a signal phase shift. The radar transceiver IC is configured to transmit a frame of chirps based on the plurality of chirp signals and generate a plurality of digital signals, each digital signal corresponding to a respective reflection received based on the plurality of chirp signals. The processor is configured to control the phase shifter to induce the signal phase shift in a first subset of chirp signals of the plurality of chirp signals and determine a phase shift induced in the first subset of chirp signals by the phase shifter based on the digital signal.
-
公开(公告)号：US11209522B2
公开(公告)日：2021-12-28
申请号：US16107000
申请日：2018-08-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sandeep Rao , Karthik Ramasubramanian
IPC: G01S7/35 , G01S13/42 , G01S13/89 , G01S13/931 , G01S13/58
Abstract: The disclosure provides a radar apparatus. The radar apparatus includes a transmitter that transmits a first chirp. The first chirp is scattered by one or more obstacles to generate a first plurality of scattered signals. A plurality of receivers receives the first plurality of scattered signals. Each receiver of the plurality of receivers generates a digital signal in response to a scattered signal of the first plurality of scattered signals. A processor is coupled to the plurality of receivers and receives the digital signals from the plurality of receivers. The processor performs range FFT (fast fourier transform) and angle FFT on the digital signals received from the plurality of receivers to generate a first matrix of complex samples.
-
公开(公告)号：US11137476B2
公开(公告)日：2021-10-05
申请号：US16120129
申请日：2018-08-31
Applicant: Texas Instruments Incorporated
Inventor： Brian Paul Ginsburg , Karthik Subburaj , Karthik Ramasubramanian , Sachin Bhardwaj , Sriram Murali , Sandeep Rao
IPC: G01S7/35 , G01S7/02 , G01S7/40 , G01S13/32 , G01S13/931
Abstract: A frequency modulated continuous wave (FMCW) radar system is provided that includes a receiver configured to generate a digital intermediate frequency (IF) signal, and an interference monitoring component coupled to the receiver to receive the digital IF signal, in which the interference monitoring component is configured to monitor at least one sub-band in the digital IF signal for interference, in which the at least one sub-band does not include a radar signal.
-
公开(公告)号：US20210248037A1
公开(公告)日：2021-08-12
申请号：US17242636
申请日：2021-04-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sandeep Rao , Karthik Ramasubramanian , Brian Paul Ginsburg
Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.
-
Patent Agency Ranking
公开(公告)号：US10775489B2
公开(公告)日：2020-09-15
申请号：US15665663
申请日：2017-08-01
Applicant: Texas Instruments Incorporated
Inventor： Sandeep Rao , Karthik Subburaj , Sriram Murali , Karthik Ramasubramanian
IPC: G01S13/28 , G06F17/14 , G01S7/41 , G01S13/536 , G01S13/931 , G01S13/34 , G01S7/35 , G06F17/13 , H04N5/232
Abstract: A radar system is provided that includes a radar transceiver integrated circuit (IC) configurable to transmit a first frame of chirps, and another radar transceiver IC configurable to transmit a second frame of chirps at a time delay ΔT, wherein ΔT=Tc/K, K≥2 and Tc is an elapsed time from a start of one chirp in the first frame and the second frame and a start of a next chirp in the first frame and the second frame, wherein the radar system is configured to determine a velocity of an object in a field of view of the radar system based on first digital intermediate frequency signals generated responsive to receiving reflected chirps of the first frame and second digital IF signals generated responsive to receiving reflected chirps of the time delayed second frame, wherein the maximum measurable velocity is increased by a factor of K.
-
公开(公告)号：US10599518B2
公开(公告)日：2020-03-24
申请号：US14985851
申请日：2015-12-31
Applicant: Texas Instruments Incorporated
Inventor： Sandeep Rao , Karthik Ramasubramanian , Brian Paul Ginsburg
Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.
-
公开(公告)号：US10598767B2
公开(公告)日：2020-03-24
申请号：US16253790
申请日：2019-01-22
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Brian Paul Ginsburg , Daniel Colum Breen , Sandeep Rao , Karthik Ramasubramanian
Abstract: Methods for monitoring of performance parameters of one or more receive channels and/or one or more transmit channels of a radar system-on-a-chip (SOC) are provided. The radar SOC may include a loopback path coupling at least one transmit channel to at least one receive channel to provide a test signal from the at least one transmit channel to the at least one receive channel when the radar SOC is operated in test mode. In some embodiments, the loopback path includes a combiner coupled to each of one or more transmit channels, a splitter coupled to each of one or more receive channels, and a single wire coupling an output of the combiner to an input of the splitter.
-
公开(公告)号：US10234542B2
公开(公告)日：2019-03-19
申请号：US14870129
申请日：2015-09-30
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Brian Paul Ginsburg , Daniel Colum Breen , Sandeep Rao , Karthik Ramasubramanian
Abstract: Methods for monitoring of performance parameters of one or more receive channels and/or one or more transmit channels of a radar system-on-a-chip (SOC) are provided. The radar SOC may include a loopback path coupling at least one transmit channel to at least one receive channel to provide a test signal from the at least one transmit channel to the at least one receive channel when the radar SOC is operated in test mode. In some embodiments, the loopback path includes a combiner coupled to each of one or more transmit channels, a splitter coupled to each of one or more receive channels, and a single wire coupling an output of the combiner to an input of the splitter.
-
公开(公告)号：US20190004167A1
公开(公告)日：2019-01-03
申请号：US16121689
申请日：2018-09-05
Applicant: Texas Instruments Incorporated
Inventor： Sandeep Rao , Karthik Subburaj , Brian Ginsburg , Karthik Ramasubramanian , Jawaharlal Tangudu , Sachin Bharadwaj
Abstract: The disclosure provides a radar apparatus for estimating a range of an obstacle. The radar apparatus includes a local oscillator that generates a first ramp segment and a second ramp segment. The first ramp segment and the second ramp segment each includes a start frequency, a first frequency and a second frequency. The first frequency of the second ramp segment is equal to or greater than the second frequency of the first ramp segment when a slope of the first ramp segment and a slope of the second ramp segment are equal and positive. The first frequency of the second ramp segment is equal to or less than the second frequency of the first ramp segment when the slope of the first ramp segment and the slope of the second ramp segment are equal and negative.
-
-
-
-
-
-
-
-
-
Search Results
116
records
(took 0.026 seconds)
