公开(公告)号：US20120016558A1

公开(公告)日：2012-01-19

申请号：US13256299

申请日：2010-03-03

申请人： Koki Ueno ,  Atsushi Kamada ,  Takahiko Tsutsumi

发明人： Koki Ueno ,  Atsushi Kamada ,  Takahiko Tsutsumi

IPC分类号： B60R25/06

CPC分类号： B60R25/08

摘要： An antitheft device for vehicle includes store means storing a parking-lock canceling state activating a parking lock canceling operation and a parking lock state disabling the parking lock canceling operation alternatively, and switching means switching the parking lock state to the parking-lock canceling state upon success of a verification, an initial value of the store means being set to the parking-lock canceling state.

摘要翻译： 用于车辆的防盗装置包括：存储装置，存储启动停车锁取消操作的停车锁取消状态和停止停车锁取消操作的停车锁定状态，切换装置将停车锁定状态切换到停车锁定取消状态 验证的成功，存储装置的初始值被设置为驻车锁定取消状态。

公开(公告)号：US07952931B2

公开(公告)日：2011-05-31

申请号：US12132426

申请日：2008-06-03

申请人： Hiroyuki Nagashima ,  Koki Ueno

发明人： Hiroyuki Nagashima ,  Koki Ueno

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/12

摘要： A nonvolatile semiconductor memory device includes a memory cell array having a plurality of cell units each including a preset number of memory cells and select gate transistors on drain and source sides. The nonvolatile semiconductor memory device includes a voltage control circuit to prevent occurrence of an erroneous write operation due to excessively high boost voltage of a channel when “1” is written into the memory cell.

摘要翻译： 非易失性半导体存储器件包括具有多个单元单元的存储单元阵列，每个单元单元包括预设数量的存储单元和漏极和源极侧的选择栅极晶体管。 非易失性半导体存储器件包括电压控制电路，用于当“1”被写入存储器单元时，防止由于通道的过高的升压电压而导致的错误写入操作的发生。

公开(公告)号：US20110007572A1

公开(公告)日：2011-01-13

申请号：US12723112

申请日：2010-03-12

申请人： Koki Ueno ,  Satoshi Uchiumi

发明人： Koki Ueno ,  Satoshi Uchiumi

IPC分类号： G11C16/06

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C2211/5621

摘要： A NAND flash memory has memory cell transistors which data is written into. If number of times the program operation has been executed is not equal to the prescribed upper limit number of times, then the program voltage is set so as to be raised by a first potential difference and then the program operation and the verify operation are executed again, andonly when the number of times of the program operation has become equal to a prescribed number of times being less than the upper limit number of times, the intermediate voltage is raised by a second potential difference and fixed.

摘要翻译： NAND闪存具有写入数据的存储单元晶体管。 如果执行程序操作的次数不等于规定的上限次数，则将编程电压设定为升高第一电位差，然后再次执行程序运行和验证操作 ，并且只有当编程操作次数已经变得等于小于上限次数的规定次数时，中间电压被提高第二电位差并且固定。

公开(公告)号：US20090268521A1

公开(公告)日：2009-10-29

申请号：US12397808

申请日：2009-03-04

申请人： Koki Ueno ,  Hiroyuki Nagashima

发明人： Koki Ueno ,  Hiroyuki Nagashima

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/349 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C29/028 ,  G11C29/50 ,  G11C29/82 ,  G11C2029/5006 ,  G11C2211/565

摘要： A non-volatile semiconductor memory device includes a non-volatile memory having a plurality of blocks each including a plurality of memory cells, a bit line electrically connected to one end of a current path of the memory cell, a source line electrically connected to the other end of the current path of the memory cell, a word line electrically connected to the gate electrode, a sense amplifier circuit electrically connected to the bit line and configured to read data from the memory cell, a row decoder electrically connected to the word line and configured to apply a read voltage at which the memory cell is set to an ON state to the word line, and a controller configured to measure a cell current flowing through the memory cell in the ON state to judge whether the memory cell has been degraded.

摘要翻译： 非挥发性半导体存储器件包括具有多个块的非易失性存储器，每个块包括多个存储器单元，电连接到存储单元的电流路径的一端的位线，电连接到存储单元的源极线 存储单元的电流路径的另一端，电连接到栅电极的字线，电连接到位线并被配置为从存储单元读取数据的读出放大器电路，电连接到字线的行解码器 并且被配置为将存储单元设置为ON状态的读取电压施加到字线，以及控制器，被配置为测量在ON状态下流过存储单元的单元电流，以判断存储单元是否已经劣化 。

公开(公告)号：US20080198668A1

公开(公告)日：2008-08-21

申请号：US12033453

申请日：2008-02-19

申请人： Koki Ueno

发明人： Koki Ueno

IPC分类号： G11C16/12

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A nonvolatile semiconductor memory according to an aspect of the invention comprises a plurality of serially connected memory cells arranged on a P-well area within a semiconductor substrate, select gate transistors connected to one end and the other of the serially connected memory cells, a P-well control circuit which controls the P-well area, a plurality of word lines connected to the plurality of memory cells, a row control circuit which controls the plurality of word lines, and an operation control circuit which controls the P-well control circuit and the row control circuit, wherein, when writing to a selected one of the plurality of memory cells, the operation control circuit controls the P-well control circuit to apply a precharge potential to the P-well area and thus precharge channel areas of the plurality of memory cells.

摘要翻译： 根据本发明的一个方面的非易失性半导体存储器包括布置在半导体衬底内的P阱区上的多个串联连接的存储单元，连接到串联存储单元的一端和另一个的选择栅极晶体管，P 控制P阱区域的多个字线，连接到多个存储单元的多个字线，控制多个字线的行控制电路以及控制P阱控制电路的操作控制电路 以及行控制电路，其中，当向所述多个存储单元中的所选择的一个存储单元进行写入时，所述操作控制电路控制所述P阱控制电路向所述P阱区域施加预充电电位， 多个存储单元。