公开(公告)号：US11205721B2

公开(公告)日：2021-12-21

申请号：US16572882

申请日：2019-09-17

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Fei Zhou

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/266 ,  H01L21/3213 ,  H01L21/02

摘要： A semiconductor device and its fabrication method are provided. The method includes providing a base substrate; forming a first well region and a second well region in the base substrate; forming a gate electrode structure, sidewall spacers, a doped source layer, a doped drain layer and a dielectric layer over the base substrate, where the doped source layer and the doped drain layer are respectively on two sides of the gate electrode structure and the sidewall spacers, and the gate electrode structure and the sidewall spacers are over the first well region and the second well region; removing a portion of the gate electrode structure on the second well region and a portion of the base substrate of the second well region to form a trench in the dielectric layer, where the trench exposes a portion of the sidewall spacers; and forming an isolation layer in the trench.

公开(公告)号：US11205703B2

公开(公告)日：2021-12-21

申请号：US16922730

申请日：2020-07-07

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Nan Wang

IPC分类号： H01L29/41 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L29/08

摘要： A semiconductor device and fabrication method thereof are provided. The method includes: providing a gate structure, a first dielectric layer, and source/drain doped layers on a base substrate and in the base substrate on sides of the gate structure; forming a mask layer on the gate structure between the source/drain doped layers; forming a second dielectric layer on the first dielectric layer and exposing the mask layer; etching the second dielectric layer and the first dielectric layer using the mask layer as an etch mask, to form first grooves on the sides of the gate structure and exposing the source/drain doped layers; forming a first conductive structure in each first groove; patterning the mask layer to form a second groove in the mask layer to expose the gate structure at the bottom of the second groove; and forming a spacer on sidewalls of the second groove.

公开(公告)号：US20210391483A1

公开(公告)日：2021-12-16

申请号：US17445879

申请日：2021-08-25

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Ming Zhou

IPC分类号： H01L31/0224 ,  H01L31/0352 ,  C01B32/184 ,  H01L21/02 ,  H01L31/02 ,  H01L31/0236 ,  H01L31/04 ,  H01L31/18

摘要： A semiconductor device includes: a conductive layer; a plurality of nanopillars spaced apart from each other overlying the conductive layer, each nanopillar comprising a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, the first semiconductor layer being different in conductivity type from the second semiconductor layer; and a graphene layer overlying the plurality of nanopillars, the graphene layer being connected to each of the plurality of nanopillars.

公开(公告)号：US20210376145A1

公开(公告)日：2021-12-02

申请号：US17400393

申请日：2021-08-12

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Deyan Chen ,  Mao Li ,  Leong Tee Koh ,  Dae-Sub Jung

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/66

摘要： The present disclosure provides an LDMOS device and a manufacturing method thereof. The LDMOS device includes: a substrate, a drift region formed in the substrate; a gate structure, located on the substrate on one side of the drift region, and covering part of the drift region; a drain region, located in the drift region on one side of the gate structure, an isolation structure located on the substrate, the isolation structure located between the drain region and the gate structure; a gate electrode, located on the gate structure and electrically connected with the gate structure; a drain electrode, located on the drain region and electrically connected with the drain region; a block layer, covering the drift region and the isolation structure between the gate electrode and the drain electrode in a shape-preserving manner; and a groove electrode located on the block layer, the groove electrode located between the isolation structure and the gate structure, and at least covering part of the top of the isolation structure. The LDMOS device improves a device breakdown voltage, and cannot increase Rdson.

公开(公告)号：US20210359126A1

公开(公告)日：2021-11-18

申请号：US17229508

申请日：2021-04-13

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Nan WANG

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

摘要： A semiconductor structure and its fabrication method are provided. The method includes: providing a substrate; forming an isolation structure on the substrate; forming a gate structure on the isolation structure; forming a first opening in the gate structure; and forming a first conductive structure in the first opening. Sidewall surfaces of the first conductive structure are in contact with a gate electrode layer of the gate structure.

公开(公告)号：US11171093B2

公开(公告)日：2021-11-09

申请号：US16703112

申请日：2019-12-04

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Zhuo Cheng ,  Xiaodong Wang

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L21/768 ,  H01L21/311

摘要： Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a wafer having a functional region and a non-functional region surrounding the functional region; forming a first dielectric layer on the wafer; forming a first opening in the first dielectric layer in the non-functional region; and forming a first connection layer in the first opening. The first connection layer closes a top portion of the first opening, and a void is formed in the first connection layer in first opening.

公开(公告)号：US20210336031A1

公开(公告)日：2021-10-28

申请号：US17220210

申请日：2021-04-01

申请人： Semiconductor Manufacturing Intenational (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Xiang HU

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/092

摘要： A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, a first gate structure over the first region, and first source-drain doped layers in the first region of the substrate on both sides of the first gate structure. The semiconductor structure also includes a second gate structure over the second region, and second source-drain doped layers in the second region of the substrate on both sides of the second gate structure. Further, the semiconductor structure includes a first protection layer over the second gate structure, a first conductive structure over a first source-drain doped layer, and an isolation layer over the first conductive structure. The first conductive structure is also formed on the first gate structure, and the first conductive structure has a top surface lower than the first protection layer.

公开(公告)号：US20210336030A1

公开(公告)日：2021-10-28

申请号：US17219982

申请日：2021-04-01

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Xiang HU

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234

摘要： A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, and a first dielectric layer, a first gate structure and a plurality of second gate structures over the substrate. A second protection layer is formed on a top of a second gate structure. A first source-drain doped layer is formed between the first gate structure and an adjacent second gate structure. The first dielectric layer covers sidewalls of the first and second gate structures, and exposes a top surface of the second protection layer. The semiconductor structure also includes a first conductive structure in the first dielectric layer over the first source-drain doped layer, and a conductive layer on the first gate structure and the first conductive structure. A top surface of the conductive layer is coplanar with a top surface of the first dielectric layer.

公开(公告)号：US11152041B2

公开(公告)日：2021-10-19

申请号：US16812531

申请日：2020-03-09

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Tao Wang ,  Xiao Zheng

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C8/10 ,  G11C29/00 ,  G06F3/06

摘要： Data reading method, device, and storage medium of a non-volatile memory are provided. The method includes obtaining address information and decoding the address information to determine an address of a corresponding memory cell; when the address of the memory cell is in a selected region, adjusting a first determination reference value to obtain a second determination reference value; applying a readout current to the memory cell, and obtaining a determination current outputted by the memory cell; and comparing a value range of the determination current outputted by the memory cell with the second determination reference value and reading out data content stored in the memory cell.

公开(公告)号：US20210320108A1

公开(公告)日：2021-10-14

申请号：US17355521

申请日：2021-06-23

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Nan WANG

IPC分类号： H01L27/11 ,  H01L21/308 ,  H01L21/265

摘要： A static random-access memory device is provided. The static random-access memory device includes a substrate with at least one first region; first fins on a surface of the substrate, and second initial fins on the surface of the substrate. A width of the second initial fins is different from a width of the first fins. A portion of the first fins is used to form pass-gate transistors, and another portion of the first fins and the second initial fins are used to form pull-down transistors.