公开(公告)号：US12218004B2

公开(公告)日：2025-02-04

申请号：US17229255

申请日：2021-04-13

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： He Zuopeng ,  Yang Ming ,  Bei Duohui

IPC: H01L21/76 ,  H01L21/033 ,  H01L21/768

Abstract: A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base; forming a pattern memory layer on the base, where at least a first trench and a second trench are provided on the pattern memory layer, where an extending direction of the first trench is parallel to an extending direction of the second trench, and the first trench and the second trench are formed using different masks; and forming mandrel lines separated on the base at positions of the base that correspond to the first trench and the second trench. By using the method, a problem that a photoresist peels off during etching due to an elongated shape when separated mandrel lines are directly formed can be avoided. Further, a problem of a relatively high requirement on a filling material when the mandrel lines are formed directly by using a plurality of photolithography processes can be avoided, to lower the requirement on the filling material.

公开(公告)号：US12068397B2

公开(公告)日：2024-08-20

申请号：US18198944

申请日：2023-05-18

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Xiang Hu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/7851

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, a first gate structure over the first region, and first source-drain doped layers in the first region of the substrate on both sides of the first gate structure. The semiconductor structure also includes a second gate structure over the second region, and second source-drain doped layers in the second region of the substrate on both sides of the second gate structure. Further, the semiconductor structure includes a first protection layer over the second gate structure, a first conductive structure over a first source-drain doped layer, and an isolation layer over the first conductive structure. The first conductive structure is also formed on the first gate structure, and the first conductive structure has a top surface lower than the first protection layer.

公开(公告)号：US20240250087A1

公开(公告)日：2024-07-25

申请号：US18562559

申请日：2021-05-19

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Jisong JIN

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878

Abstract: A semiconductor structure includes a substrate including a first region. The first region includes a plurality of first active regions arranged along a first direction and a first isolation region between the adjacent first active regions. The semiconductor structure also includes a plurality of first fins on the substrate, parallel to the first direction and arranged along a second direction. The second direction is perpendicular to the first direction. The first fins span the adjacent first active regions and the first isolation region between the first active regions. The semiconductor structure also includes a plurality of first gate structures in the first isolation region. The first gate structures span the first fins along the second direction. The semiconductor structure also includes a plurality of first electrical interconnection structures, electrically connected to the first gate structures.

公开(公告)号：US12048133B2

公开(公告)日：2024-07-23

申请号：US17746693

申请日：2022-05-17

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Nan Wang

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B10/12 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate having at least one first region, a plurality of second regions and a plurality of third regions; at least one second fin formed on one second region of the plurality of second region; at least one third fin formed on one third region of the plurality of third regions; a first epitaxial layer formed in the at least one first fin; and a second epitaxial layer formed in the at least one second fin and the at least one third fin.

公开(公告)号：US20240222415A1

公开(公告)日：2024-07-04

申请号：US18684125

申请日：2021-08-20

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Siriguleng ZHANG

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/1465 ,  H01L24/08 ,  H01L24/80 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A photoelectric sensor includes: isolation structures in a pixel substrate between photosensitive units and including conductive layers; interconnection structures distributed in the pixel substrate with ends exposed on a second surface, including first interconnection structures in a first lead area and second interconnection structures in a second lead area and electrically connected to the first interconnection structures; a metal grid located on and in contact with the conductive layers on the second surface; a connection layer on the second surface in the first lead area and in contact with the metal grid and the first interconnection structures; and pad layers on the second surface in the lead area. The pad layers include a first pad layer in the second lead area and in contact with ends of the second interconnection structures facing the second surface.

公开(公告)号：US11921318B2

公开(公告)日：2024-03-05

申请号：US17742974

申请日：2022-05-12

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Xiaojun Chen ,  Honglin Zeng ,  Xia Feng ,  Dongsheng Zhang ,  Xiage Yin ,  Jiaheng Wu

IPC: G02B6/124 ,  G02B6/12 ,  G02B6/13

CPC classification number: G02B6/12004 ,  G02B6/124 ,  G02B6/13 ,  G02B2006/12061

Abstract: A method of forming a semiconductor structure includes: providing an initial substrate having a first region and a second region; forming a first substrate on the initial substrate; forming a first insulating layer on the first substrate; forming a second substrate on the first insulating layer; removing the second substrate in the second region to form a second insulating layer on the first insulating layer in the second region; and forming a plurality of passive devices on the second insulating layer in the second region and forming a plurality of active devices on the second substrate in the first region.

公开(公告)号：US20240006514A1

公开(公告)日：2024-01-04

申请号：US18038106

申请日：2020-11-27

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Nan WANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/6656 ,  H01L29/0847

Abstract: A semiconductor structure and fabrication method are provided. The fabrication method includes providing a substrate and a fin protruding from the substrate, the fin including stacked structures and each stacked structure including a sacrificial layer and a semiconductor layer on the sacrificial layer; forming a dummy gate across the fin; etching the fin on two sides of the dummy gate to form source/drain recesses; etching the sacrificial layer of the fin at the bottom of the dummy gate exposed by the source/drain recesses to form auxiliary recesses along an extension direction of the fin; forming an isolation layer on the bottoms of the auxiliary recesses without completely filling the auxiliary recesses; and forming a source/drain doped layer completely filling the source/drain recesses, the source/drain doped layer and the isolation layer enclosing an air gap.

公开(公告)号：US20240004320A1

公开(公告)日：2024-01-04

申请号：US18368094

申请日：2023-09-14

Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION

Inventor： Wei Hua SANG ,  Shi Jie WU ,  Bin XING

IPC: G03F9/00

CPC classification number: G03F9/708 ,  G03F9/7076

Abstract: A mask plate, an alignment mark and a photolithography system are provided. In one form, an alignment mark includes a plurality of alignment patterns arranged at intervals, where the alignment pattern includes a first pattern extending in a first direction and a second pattern extending in a second direction, the first pattern includes a first end and a second end which are opposite to each other in the first direction, the second pattern includes a third end and a fourth end which are opposite to each other in the second direction, the second end is connected to the third end, the fourth end is connected to the first end, and the alignment pattern is a two-dimensional linear pattern.

公开(公告)号：US11810860B2

公开(公告)日：2023-11-07

申请号：US17249011

申请日：2021-02-17

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Nan Wang

IPC: H01L23/532 ,  H01L29/66 ,  H01L29/40 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L21/762 ,  H01L21/768 ,  H10B10/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L23/53295 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66545 ,  H10B10/12 ,  H01L29/086 ,  H01L29/0878

Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate; and a first gate structure and doped source/drain layers on the base substrate. The doped source/drain layers are on both sides of the first gate structure. The semiconductor device further includes a dielectric layer on a surface of the base substrate. The dielectric layer covers the doped source/drain layers, and the dielectric layer contains a first trench on the doped source/drain layer. The first trench includes a first region filled by an insulation layer and a second region filled by first conductive structure under the insulation layer. A top size of the insulation layer in the first region is larger than a bottom size of the insulation layer in the first region. A maximum size of the first conductive structure in the second region is smaller than the bottom size of the insulation layer in the first region.

公开(公告)号：US11808975B2

公开(公告)日：2023-11-07

申请号：US17646125

申请日：2021-12-27

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Jun Liu ,  Hong Gang Dai ,  Dong Xiang Cheng

IPC: G02B6/12 ,  G02B6/10 ,  G02B6/122 ,  G02B6/136

CPC classification number: G02B6/122 ,  G02B6/136 ,  G02B2006/12061

Abstract: A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate, an optical waveguide layer over the base substrate; a first dielectric layer over the base substrate; a cavity between the first dielectric layer and the optical waveguide layer; and a second dielectric layer on the first dielectric layer and the optical waveguide layer. The cavity is located on sidewall surfaces of the optical waveguide layer and has a bottom coplanar with a bottom of the optical waveguide layer. The second dielectric layer is located on a top of the cavity and seals the cavity.