公开(公告)号：US20180081919A1

公开(公告)日：2018-03-22

申请号：US15815772

申请日：2017-11-17

Applicant: Ab Initio Technology LLC

Inventor： Craig W. Stanfill ,  Richard Shapiro ,  Stephen A. Kukolich

IPC: G06F17/30 ,  G06F9/44 ,  G06F9/45 ,  G06F9/50

CPC classification number: G06F16/22 ,  G06F8/41 ,  G06F8/433 ,  G06F8/456 ,  G06F9/4494 ,  G06F9/5066 ,  G06F16/9024

Abstract: A graph-based program specification includes: a plurality of components, each corresponding to a processing task and including one or more ports, including scalar data ports for sending or receiving a single data element and collection data ports for sending or receiving a collection of multiple data elements; and one or more links, each connecting an output port of an upstream component to an input port of a downstream component. Prepared code is generated representing subsets of the plurality of components, including: identifying one or more subset boundaries, including identifying one or more links connecting a collection data port of a component to a scalar data port of a component; forming the subsets based on the identified subset boundaries; and generating prepared code for each formed subset that when used for execution by a runtime system causes processing tasks corresponding to the components in each formed subset to be performed.

公开(公告)号：US20180081648A1

公开(公告)日：2018-03-22

申请号：US15469176

申请日：2017-03-24

Applicant: Oracle International Corporation

Inventor： Vicente A. Romero Zaldivar ,  Maurizio Cimadamore ,  Jonathan J. Gibbons

IPC: G06F9/45 ,  G06F9/455

CPC classification number: G06F9/4552 ,  G06F8/433 ,  G06F8/437 ,  G06F9/44521

Abstract: Operations include determining a compile-time representation of a particular type. A request for the compile-time representation of the particular type comprises a source representation of the particular type. Based on and subsequent to receiving the request, a source representation of a source code file comprising the source representation of the particular type is generated. The source representation of the source code file is converted to a compile-time representation of the source code file. The compile-time representation of the particular type is derived from the source time representation of the source code file. The source code file may also be compiled to generate a set of compiled code. The set of compiled code may be loaded into a virtual machine for generating a runtime representation of the set of compiled code. A runtime representation of the particular type is derived from the runtime representation of the set of compiled code.

公开(公告)号：US20180074798A1

公开(公告)日：2018-03-15

申请号：US15701105

申请日：2017-09-11

Applicant: CANON KABUSHIKI KAISHA

Inventor： JUDE ANGELO AMBROSE ,  ALEX NYIT CHOY YEE ,  IFTEKHAR AHMED

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F8/35 ,  G06F8/433 ,  G06F8/443 ,  G06F8/4434 ,  G06F8/4441 ,  G06F8/71 ,  G06F8/75 ,  G06F8/77

Abstract: A method of selecting a software code optimisation for a section of algorithm software code in order to modify resource usage of hardware, the method comprising the steps of classifying each of a plurality of software code optimisations each characterising modifications to the section of software code that modify the hardware resource usage, forming combinations of the software code optimisations, each containing at least two of the software code optimisations and being formed according to an interdependency of the optimisation techniques of the software code optimisations in the combination, wherein the software code optimisations of each combination are useable together, and modifying the section of software code with at least two of the software code optimisations belonging to a selected combination of the set of combinations in order to modify the resource usage of the hardware executing the section of software code.

公开(公告)号：US09910646B2

公开(公告)日：2018-03-06

申请号：US14998274

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Abhay S. Kanhere ,  Haitao Feng ,  Paul H Hohensee ,  Aravind Subramanian

IPC: G06F9/45

CPC classification number: G06F8/433 ,  G06F8/53

Abstract: Technologies for native code invocation using binary analysis are described. A computing device for invoking native code from managed code using binary analysis receives a call from a thread executing a managed code segment to execute a native code segment. The computing device performs a binary analysis of the native code segment and generates, from the binary analysis, a complexity indicator that indicates a level of complexity of the native code segment by comparing the native code segment to at least one predefined complexity rule. Additionally, the computing device stores a status of the thread based on the complexity indicator and executes the native code segment. Other embodiments are described and claimed.

公开(公告)号：US20180046441A1

公开(公告)日：2018-02-15

申请号：US15549785

申请日：2016-02-09

Applicant: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK

Inventor： Fang-hsiang Su Su ,  Lakshminarasimhan Sethumadhavan ,  Gail E. Kaiser ,  Tony Jebara

IPC: G06F9/45

CPC classification number: G06F8/433

Abstract: Disclosed are devices, systems, apparatus, methods, products, media, and other implementations, including a method that includes generating for a code segment of a first process an instruction dependency graph representative of behavior of the first process, obtaining respective one or more instruction dependency graphs representative of behaviors of code segments for one or more other processes, and determining, based on the first instruction dependency graph for the first process and the respective one or more instruction dependency graphs for the one or more other processes, a level of similarity between the first process and at least one of the one or more other processes.

公开(公告)号：US20180046440A1

公开(公告)日：2018-02-15

申请号：US15555643

申请日：2016-03-03

Applicant: Ingo Josopait

Inventor： Ingo Josopait

IPC: G06F9/45

CPC classification number: G06F8/423 ,  G06F8/314 ,  G06F8/433 ,  G06F8/434 ,  G06F9/4494

Abstract: The present invention discloses a method of flow control in a computing device, for processing of flow control statements to adapt a data structure of a program running on the computing device and a computer program product storing the method. The invention thereby allows the integration of the kernels into the main program when compiling. The whole parsing of the CPU program parts and the kernels is done by 10 one single standard compiler. The actual compiler for the device can be linked as a library and does not need to do any parsing. The invention further allows loops and if-clauses to be used in language-embedded GPGPU programming, enabling full general-purpose programming of the device in a way that is fully embedded in an ordinary programming language. The device can be a highly parallel computing 15 device, such as a video card, or some other computing device.

公开(公告)号：US09875101B1

公开(公告)日：2018-01-23

申请号：US15238879

申请日：2016-08-17

Applicant: MARVELL INTERNATIONAL LTD.

Inventor： Xinyu Qi ,  Liping Gao ,  Haitao Huang ,  XingXing Pan ,  Pengfei Li

IPC: G06F9/45 ,  G06F9/30

CPC classification number: G06F8/433

Abstract: Aspects of the disclosure provide a method for identifying an induction variable in a loop during a compiling process. The method includes searching for a phi-function that includes a first operand and a second operand and defines a candidate basic induction variable (BIV), searching for an add/sub instruction that has a first register and a second register wherein the first register is the second operand of the phi-function, or the value in the first register is subsequently stored to the second operand of the phi-function through one or more move instructions, and determining the candidate BIV is a BIV when the second register of the add/sub instruction is the candidate BIV or stores a value that is passed from the candidate BIV through one or more move instructions.

公开(公告)号：US09804829B2

公开(公告)日：2017-10-31

申请号：US15087116

申请日：2016-03-31

Applicant: CA, Inc.

Inventor： Josiah Daniel Haswell ,  James Andrew Perkins

IPC: G06F9/45

CPC classification number: G06F8/436 ,  G06F8/40 ,  G06F8/41 ,  G06F8/42 ,  G06F8/433 ,  G06F8/71

Abstract: An interface definition language compiler can be designed to generate different versions of stubs or library files from a same IDL source code. A developer can maintain a single IDL file with code for various versions by using version directives. As part of front end compiling, the IDL compiler will determine which sections of IDL code are compatible with a specified version and compile those determined sections of IDL code. When performing semantic analysis, the IDL compiler will determine whether changes across versions create semantic issues that can be resolved in the target program language by the backend of the compiler. For those changes that cannot be resolved in the target program language, the IDL compiler can generate error notifications.

公开(公告)号：US09754344B2

公开(公告)日：2017-09-05

申请号：US14645210

申请日：2015-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： John W. Brothers ,  Santosh Abraham

IPC: G06T11/00 ,  H04N19/00 ,  H04N19/176 ,  G06F9/45 ,  G06F9/38 ,  G06T1/60 ,  G09G5/36 ,  G09G5/393 ,  G06T11/40

CPC classification number: G06T1/60 ,  G06F8/433 ,  G06F9/3838 ,  G06T11/40 ,  G09G5/363 ,  G09G5/393 ,  G09G2350/00 ,  G09G2360/121

Abstract: A graphics processing operation may include a set of render target operations, in which render targets are read and one or more intermediate computations are performed before generating final render target output. A method of performing graphics processing includes determining a dependency between render targets and defining a scheduling of tiles to reduce or eliminate a need to write intermediate computations to external memory. An interleaved order may be determined to maintain intermediate computations of dependent render target operations in an on-chip cache hierarchy.

公开(公告)号：US09753727B2

公开(公告)日：2017-09-05

申请号：US13995721

申请日：2012-10-25

Applicant: Intel Corporation

Inventor： Tin-Fook Ngai ,  Chunxiao Lin ,  Yingzhe Shen ,  Chao Zhang

IPC: G06F9/30 ,  G06F9/45

CPC classification number: G06F9/30036 ,  G06F8/433 ,  G06F8/4441 ,  G06F8/452

Abstract: Generally, this disclosure provides technologies for generating and executing partially vectorized code that may include backward dependencies within a loop body of the code to be vectorized. The method may include identifying backward dependencies within a loop body of the code; selecting one or more ranges of iterations within the loop body, wherein the selected ranges exclude the identified backward dependencies; and vectorizing the selected ranges. The system may include a vector processor configured to provide predicated vector instruction execution, loop iteration range enabling, and dynamic loop dependence checking.