FIRMWARE VERIFICATION MECHANISM
    1.
    发明申请

    公开(公告)号:US20220327214A1

    公开(公告)日:2022-10-13

    申请号:US17852814

    申请日:2022-06-29

    Abstract: An apparatus to verify firmware in a computing system, comprising a non-volatile memory, including firmware memory to store agent firmware associated with each of a plurality of interconnect protocol (IP) agents and version memory to store security version numbers (SVNs) included in the agent firmware, a security controller comprising verifier logic to verify an integrity of the version memory by applying a hash algorithm to contents of the version memory to generate a SVN hash, and a trusted platform module (TPM) to store the SVN hash.

    FIRMWARE VERIFICATION MECHANISM
    2.
    发明申请

    公开(公告)号:US20240378294A1

    公开(公告)日:2024-11-14

    申请号:US18426561

    申请日:2024-01-30

    Abstract: An apparatus to verify firmware in a computing system, comprising a non-volatile memory, including firmware memory to store agent firmware associated with each of a plurality of interconnect protocol (IP) agents and version memory to store security version numbers (SVNs) included in the agent firmware, a security controller comprising verifier logic to verify an integrity of the version memory by applying a hash algorithm to contents of the version memory to generate a SVN hash, and a trusted platform module (TPM) to store the SVN hash.

    Partial vectorization compilation system

    公开(公告)号:US09753727B2

    公开(公告)日:2017-09-05

    申请号:US13995721

    申请日:2012-10-25

    CPC classification number: G06F9/30036 G06F8/433 G06F8/4441 G06F8/452

    Abstract: Generally, this disclosure provides technologies for generating and executing partially vectorized code that may include backward dependencies within a loop body of the code to be vectorized. The method may include identifying backward dependencies within a loop body of the code; selecting one or more ranges of iterations within the loop body, wherein the selected ranges exclude the identified backward dependencies; and vectorizing the selected ranges. The system may include a vector processor configured to provide predicated vector instruction execution, loop iteration range enabling, and dynamic loop dependence checking.

    FIRMWARE VERIFICATION MECHANISM
    9.
    发明申请

    公开(公告)号:US20200226261A1

    公开(公告)日:2020-07-16

    申请号:US16832152

    申请日:2020-03-27

    Abstract: An apparatus to verify firmware in a computing system, comprising a non-volatile memory, including firmware memory to store agent firmware associated with each of a plurality of interconnect protocol (IP) agents and version memory to store security version numbers (SVNs) included in the agent firmware, a security controller comprising verifier logic to verify an integrity of the version memory by applying a hash algorithm to contents of the version memory to generate a SVN hash, and a trusted platform module (TPM) to store the SVN hash.

    User interface for liquid container

    公开(公告)号:US10120563B2

    公开(公告)日:2018-11-06

    申请号:US14779524

    申请日:2014-12-24

    Abstract: A container, such as a beverage container or a mug, may include electronics to run applications. In some examples, the container may include a display for visually displaying icons, menus, data, and other elements. In some examples, the container may include one or more sensors, such as touch sensitivity built into the display or a separate touch-sensitive panel, and/or a motion sensor. In some examples, the container may use the one or more sensors to receive input from a user to run interactive applications on the display. In some examples, the container may recognize particular forms of input, such as user swipes in specified directions and/or for specified durations on the touch-sensitive display, and/or motion of the container in specified directions to execute specified commands for the applications. The recognized input may form a user interface for the user.

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