公开(公告)号：US20130169368A1

公开(公告)日：2013-07-04

申请号：US13340790

申请日：2011-12-30

Applicant: Syed Enam Rehman

Inventor： Syed Enam Rehman

IPC: H03L7/08 ,  H03B5/12

CPC classification number: H03L7/00 ,  H03B1/00 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/0062 ,  H03L1/023 ,  H03L7/18

Abstract: Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function.

Abstract translation: RCL谐振电路中的电容调整通常通过调整施加到电容器一侧的直流电压来进行。 电容器的一侧通常连接到RCL谐振电路中的再生电路的输出节点或栅极。 谐振电路的电容成为由谐振电路产生的直流电压和交流正弦信号的函数。 通过电容耦合电容器的两个节点，DC电压可以在输出波形的全摆幅时控制电容器的值。 此外，代替RCL谐振电路驱动负载输出的单个差分功能，每个输出驱动独立的单端功能; 从而提供两个同时的操作来代替一个差分功能。

公开(公告)号：US20130076408A1

公开(公告)日：2013-03-28

申请号：US13243908

申请日：2011-09-23

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H03B19/00 ,  H03F3/45

CPC classification number: H03K21/023 ,  H03L7/193

Abstract: A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

Abstract translation: 锁相环（PLL）是无线系统中的重要组成部分。 CMOS技术提供工作在60 GHz的压控振荡器设计。 其中一个困难是使用传统的CMOS将高频时钟降低到可管理的时钟频率。 虽然注入锁定分频器可以分频此时钟频率，但这些分频器有局限性。 提出了使用几种技术的除以2; 前馈，时钟放大和串联峰值电感，以克服这些局限性。

公开(公告)号：US08406710B1

公开(公告)日：2013-03-26

申请号：US13243986

申请日：2011-09-23

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H01Q11/12 ,  H04K3/00

CPC classification number: H01Q11/12

Abstract: Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.

Abstract translation: 超高频电路遭受寄生电阻。 在60GHz，传统的布局技术可以在关键位置引入电路损耗。 预驱动器的输出和最终输出级的栅极之间的一个关键互连会导致由于布局导致1或2 dB的损耗。 通过最小化通孔触点的数量，可以使用这种新的布局技术来恢复传统的损耗。 此外，使用通孔堆叠的抽头点来修改互连的谐振特性。 最后，谐振电路中的交叉耦合器件用于以共模增益为代价来降低共模噪声。

公开(公告)号：US20120002702A1

公开(公告)日：2012-01-05

申请号：US13151246

申请日：2011-06-01

Applicant: Ismail Lakkis ,  Hock Law

Inventor： Ismail Lakkis ,  Hock Law

IPC: H04L27/00 ,  H04B1/69

CPC classification number: H04L27/00 ,  G01S1/20 ,  G01S5/0226 ,  G01S5/0289 ,  G01S5/10 ,  H04B1/69

Abstract: A positioning system comprises a plurality of controllers, each controller comprising a wideband receiver and a narrow band transmitter, the each controller configured to receive a wideband positioning frame using the wideband receiver from one or more devices and to transmit acknowledgement frames using the narrow band transmitter that include timing and control data for use by the devices to establish timing for transmission of the positioning frame; and at least one device comprising a wideband transmitter and a narrow band receiver, the device configured to transmit a positioning frame to the plurality of controllers using the wideband transmitter and to receive an acknowledgement frame from one or more controllers using the narrow band receiver, extract timing and control information from the frame, and adjust the timing and synchronization of the wideband transmitter using the timing and control information.

Abstract translation: 定位系统包括多个控制器，每个控制器包括宽带接收机和窄带发射机，每个控制器被配置为使用来自一个或多个设备的宽带接收机接收宽带定位帧，并使用窄带发射机发送确认帧 其包括由设备使用以建立定位框架的传输定时的定时和控制数据; 以及包括宽带发射机和窄带接收机的至少一个设备，所述设备被配置为使用所述宽带发射机向所述多个控制器发送定位帧并且使用所述窄带接收机从一个或多个控制器接收确认帧，提取 来自帧的定时和控制信息，并且使用定时和控制信息来调整宽带发射机的定时和同步。