公开(公告)号：US20050195003A1

公开(公告)日：2005-09-08

申请号：US10794189

申请日：2004-03-05

申请人： Zaw Soe

发明人： Zaw Soe

IPC分类号： G05F1/10 ,  G05F3/02 ,  H02M3/18 ,  H02M7/25 ,  H03L7/00 ,  H03L7/06

CPC分类号： H03L7/0896

摘要： A charge pump circuit utilizes active feedback control circuits to control the currents produced by sinking and sourcing current sources. The feedback control circuits may regulate the drain voltages of sinking and sourcing current source transistors to make them approximately equal to respective reference voltages received by the feedback control circuits. The charge pump circuit may utilize multiple supply voltages, with a higher supply voltage such as a 3.3 V supply voltage being used to drive current source transistors, and a lower supply voltage such as a 1.8 V supply voltage being used to drive switches in a switching section.

公开(公告)号：US08680899B2

公开(公告)日：2014-03-25

申请号：US13243908

申请日：2011-09-23

申请人： Zaw Soe

发明人： Zaw Soe

IPC分类号： H03B19/00

CPC分类号： H03K21/023 ,  H03L7/193

摘要： A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

摘要翻译： 锁相环（PLL）是无线系统中的重要组成部分。 CMOS技术提供工作在60 GHz的压控振荡器设计。 其中一个困难是使用传统的CMOS将高频时钟降低到可管理的时钟频率。 虽然注入锁定分频器可以分频此时钟频率，但这些分频器有局限性。 提出了使用几种技术的除以2; 前馈，时钟放大和串联峰值电感，以克服这些局限性。

公开(公告)号：US20130078933A1

公开(公告)日：2013-03-28

申请号：US13243986

申请日：2011-09-23

申请人： Zaw Soe

发明人： Zaw Soe

IPC分类号： H04W88/02 ,  H03B11/00

CPC分类号： H01Q11/12

摘要： Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.

摘要翻译： 超高频电路遭受寄生电阻。 在60GHz，传统的布局技术可以在关键位置引入电路损耗。 预驱动器的输出和最终输出级的栅极之间的一个关键互连会导致由于布局导致1或2 dB的损耗。 通过最小化通孔触点的数量，可以使用这种新的布局技术来恢复传统的损耗。 此外，使用通孔堆叠的抽头点来修改互连的谐振特性。 最后，谐振电路中的交叉耦合器件用于以共模增益为代价来降低共模噪声。

公开(公告)号：US20120319673A1

公开(公告)日：2012-12-20

申请号：US13163562

申请日：2011-06-17

申请人： KhongMeng Tham ,  Zaw Soe

发明人： KhongMeng Tham ,  Zaw Soe

IPC分类号： G05F3/02

CPC分类号： H03K3/012 ,  G05F3/16 ,  H01Q1/50 ,  H03K17/56 ,  H04B5/0075

摘要： This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

摘要翻译： 当设计高频（〜60GHz）电路时，本发明消除了对电容器耦合或变压器耦合的需要，以及与这些耦合技术相关联的不期望的寄生电容和电感。 在这个频率下，两个相邻阶段之间的距离需要最小化。 与电源或接地引线串联的谐振电路用于将偏置信号与高频信号隔离开来。 该谐振电路的引入允许第一级使用金属迹线直接耦合到下一级。 直接耦合技术将高频信号和偏置电压都通过下一级。 与AC耦合或变压器耦合方法相比，直接耦合方法克服了大的管芯面积使用，因为电容器和变压器都不需要在级之间传输高频信号。

公开(公告)号：US20070155350A1

公开(公告)日：2007-07-05

申请号：US11322073

申请日：2005-12-29

申请人： Behzad Razavi ,  Zaw Soe

发明人： Behzad Razavi ,  Zaw Soe

IPC分类号： H03J7/32

CPC分类号： H03J1/0008 ,  H03D7/165

摘要： The present invention provides reduces the number of required synthesizers thereby reducing the area and power concerns to extract/insert a signal from/to a multi-channel communication system and is also known as frequency planning. The highest frequency of operation required for the synthesizers or oscillators is approximately the midpoint of the entire signal frequency range. Two superimposed Weaver architectures are used to form the architecture. The receiver extracts the baseband I and Q signals from the multi-channel communication system, while the transmitter upconverts the baseband I and Q signals to the multi-channel communication system. The Weaver architecture, depending on the select bit, can enhance the image signal and reduce the desired signal or the image signal can be reduced while the desired signal is enhanced. Because the image and signal components are symmetrically displaced from the RF LO, less IF LO frequencies or synthesizers are required to operate the system.

摘要翻译： 本发明减少了所需的合成器的数量，从而减少了从多通道通信系统提取/插入信号的面积和功率问题，也被称为频率规划。 合成器或振荡器所需的最高运行频率大约是整个信号频率范围的中点。 两个叠加的Weaver架构被用来形成架构。 接收机从多通道通信系统中提取基带I和Q信号，而发射机将基带I和Q信号上变频到多通道通信系统。 取决于选择位的韦弗架构可以增强图像信号并减少所需信号，或者可以在所需信号增强的同时降低图像信号。 由于图像和信号分量从RF LO对称地移位，因此需要较少的IF LO频率或合成器来操作系统。

公开(公告)号：US08626106B2

公开(公告)日：2014-01-07

申请号：US13312806

申请日：2011-12-06

申请人： Zaw Soe

发明人： Zaw Soe

IPC分类号： H04B1/16 ,  H03F3/19

CPC分类号： H03F1/42 ,  H03D7/125 ,  H03D7/1441 ,  H03D7/1466 ,  H03D7/165 ,  H03F1/223 ,  H03F3/193 ,  H03F3/387 ,  H03F3/45071 ,  H03F3/45179 ,  H03F2200/108 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H03F2200/72 ,  H03F2200/75 ,  H04L27/38

摘要： A cascode common source and common gate LNAs operating at 60 GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra.

摘要翻译： 引入并描述了以60GHz操作的共源共栅和公共栅极LNA。 对共源共栅源LNA进行模拟，以达到上部器件宽度与较低器件宽度的最佳比例。 共源共栅源LNA的电压输出转换为电流以馈送并将能量施加到混频器级。 这些输入电流信号将与电流相关联的能量直接施加到混频器中的开关电容器中，以最小化系统的总功耗。 LNA电容耦合到I和Q混频器中的混频器开关，并由正交振荡器产生的时钟使能和禁止。 然后，这些信号被差分放大器放大以产生和和差频谱。

公开(公告)号：US20130076408A1

公开(公告)日：2013-03-28

申请号：US13243908

申请日：2011-09-23

申请人： Zaw Soe

发明人： Zaw Soe

IPC分类号： H03B19/00 ,  H03F3/45

CPC分类号： H03K21/023 ,  H03L7/193

摘要： A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

摘要翻译： 锁相环（PLL）是无线系统中的重要组成部分。 CMOS技术提供工作在60 GHz的压控振荡器设计。 其中一个困难是使用传统的CMOS将高频时钟降低到可管理的时钟频率。 虽然注入锁定分频器可以分频此时钟频率，但这些分频器有局限性。 提出了使用几种技术的除以2; 前馈，时钟放大和串联峰值电感，以克服这些局限性。

公开(公告)号：US08406710B1

公开(公告)日：2013-03-26

申请号：US13243986

申请日：2011-09-23

申请人： Zaw Soe

发明人： Zaw Soe

IPC分类号： H01Q11/12 ,  H04K3/00

CPC分类号： H01Q11/12

摘要： Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.

摘要翻译： 超高频电路遭受寄生电阻。 在60GHz，传统的布局技术可以在关键位置引入电路损耗。 预驱动器的输出和最终输出级的栅极之间的一个关键互连会导致由于布局导致1或2 dB的损耗。 通过最小化通孔触点的数量，可以使用这种新的布局技术来恢复传统的损耗。 此外，使用通孔堆叠的抽头点来修改互连的谐振特性。 最后，谐振电路中的交叉耦合器件用于以共模增益为代价来降低共模噪声。

公开(公告)号：US20070236267A1

公开(公告)日：2007-10-11

申请号：US11398278

申请日：2006-04-05

申请人： Behzad Razavi ,  Zaw Soe

发明人： Behzad Razavi ,  Zaw Soe

IPC分类号： H03K3/00

CPC分类号： H03K3/012 ,  H03K3/356043

摘要： The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.

摘要翻译： 本发明的技术可以动态地调节在预分频器或分频器的组件内施加的电流。 电流的这种动态缩放可以将分频器的速度提高一倍，或者将传统的预分频器的平均电流减小一半。 逆变器用于直接调整电流的动态值。 常规电路中的常规NMOS器件的去除消除了CML预分频器中的一个门延迟。 第二，本发明的预分频器电路在当前的注入/提取技术下工作。 与驱动整个常规预分频器的大型缓冲器相比，一组小型匹配的反相器可以在整个预分频器内单独驱动每个电流开关电路。 最后，动态电流扩展为设计人员提供了额外的灵活性，可以在施加到负载的最大电流和实现最大性能之间进行折衷。

公开(公告)号：US20070218851A1

公开(公告)日：2007-09-20

申请号：US11804516

申请日：2007-05-16

申请人： Zaw Soe ,  Tony Yang ,  Jackie Cheng ,  Sining Zhou ,  Kuangyu Li ,  Fei-Ran Yang ,  Shoufang Chen ,  Tom Baker

发明人： Zaw Soe ,  Tony Yang ,  Jackie Cheng ,  Sining Zhou ,  Kuangyu Li ,  Fei-Ran Yang ,  Shoufang Chen ,  Tom Baker

IPC分类号： H04B1/16

CPC分类号： H04B1/403

摘要： Multistage RF transmitter and receiver circuits may use independently variable RF and IF local oscillators, allowing the RF and IF local oscillator frequencies for a given RF channel to be selected to have a large common factor with respect to the reference oscillator used by the local oscillator circuits, thus allowing the use of small divisor numbers in the local oscillator circuits and reducing phase noise. Independent high-side and low-side RF local oscillators may be provided and selectively used depending on the RF channel to be transmitted or received.