公开(公告)号：US20050195003A1

公开(公告)日：2005-09-08

申请号：US10794189

申请日：2004-03-05

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: G05F1/10 ,  G05F3/02 ,  H02M3/18 ,  H02M7/25 ,  H03L7/00 ,  H03L7/06

CPC classification number: H03L7/0896

Abstract: A charge pump circuit utilizes active feedback control circuits to control the currents produced by sinking and sourcing current sources. The feedback control circuits may regulate the drain voltages of sinking and sourcing current source transistors to make them approximately equal to respective reference voltages received by the feedback control circuits. The charge pump circuit may utilize multiple supply voltages, with a higher supply voltage such as a 3.3 V supply voltage being used to drive current source transistors, and a lower supply voltage such as a 1.8 V supply voltage being used to drive switches in a switching section.

公开(公告)号：US08680899B2

公开(公告)日：2014-03-25

申请号：US13243908

申请日：2011-09-23

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H03B19/00

CPC classification number: H03K21/023 ,  H03L7/193

Abstract: A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

Abstract translation: 锁相环（PLL）是无线系统中的重要组成部分。 CMOS技术提供工作在60 GHz的压控振荡器设计。 其中一个困难是使用传统的CMOS将高频时钟降低到可管理的时钟频率。 虽然注入锁定分频器可以分频此时钟频率，但这些分频器有局限性。 提出了使用几种技术的除以2; 前馈，时钟放大和串联峰值电感，以克服这些局限性。

公开(公告)号：US20130078933A1

公开(公告)日：2013-03-28

申请号：US13243986

申请日：2011-09-23

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H04W88/02 ,  H03B11/00

CPC classification number: H01Q11/12

Abstract: Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.

Abstract translation: 超高频电路遭受寄生电阻。 在60GHz，传统的布局技术可以在关键位置引入电路损耗。 预驱动器的输出和最终输出级的栅极之间的一个关键互连会导致由于布局导致1或2 dB的损耗。 通过最小化通孔触点的数量，可以使用这种新的布局技术来恢复传统的损耗。 此外，使用通孔堆叠的抽头点来修改互连的谐振特性。 最后，谐振电路中的交叉耦合器件用于以共模增益为代价来降低共模噪声。

公开(公告)号：US20120319673A1

公开(公告)日：2012-12-20

申请号：US13163562

申请日：2011-06-17

Applicant: KhongMeng Tham ,  Zaw Soe

Inventor： KhongMeng Tham ,  Zaw Soe

IPC: G05F3/02

CPC classification number: H03K3/012 ,  G05F3/16 ,  H01Q1/50 ,  H03K17/56 ,  H04B5/0075

Abstract: This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

Abstract translation: 当设计高频（〜60GHz）电路时，本发明消除了对电容器耦合或变压器耦合的需要，以及与这些耦合技术相关联的不期望的寄生电容和电感。 在这个频率下，两个相邻阶段之间的距离需要最小化。 与电源或接地引线串联的谐振电路用于将偏置信号与高频信号隔离开来。 该谐振电路的引入允许第一级使用金属迹线直接耦合到下一级。 直接耦合技术将高频信号和偏置电压都通过下一级。 与AC耦合或变压器耦合方法相比，直接耦合方法克服了大的管芯面积使用，因为电容器和变压器都不需要在级之间传输高频信号。

公开(公告)号：US20070155350A1

公开(公告)日：2007-07-05

申请号：US11322073

申请日：2005-12-29

Applicant: Behzad Razavi ,  Zaw Soe

Inventor： Behzad Razavi ,  Zaw Soe

IPC: H03J7/32

CPC classification number: H03J1/0008 ,  H03D7/165

Abstract: The present invention provides reduces the number of required synthesizers thereby reducing the area and power concerns to extract/insert a signal from/to a multi-channel communication system and is also known as frequency planning. The highest frequency of operation required for the synthesizers or oscillators is approximately the midpoint of the entire signal frequency range. Two superimposed Weaver architectures are used to form the architecture. The receiver extracts the baseband I and Q signals from the multi-channel communication system, while the transmitter upconverts the baseband I and Q signals to the multi-channel communication system. The Weaver architecture, depending on the select bit, can enhance the image signal and reduce the desired signal or the image signal can be reduced while the desired signal is enhanced. Because the image and signal components are symmetrically displaced from the RF LO, less IF LO frequencies or synthesizers are required to operate the system.

Abstract translation: 本发明减少了所需的合成器的数量，从而减少了从多通道通信系统提取/插入信号的面积和功率问题，也被称为频率规划。 合成器或振荡器所需的最高运行频率大约是整个信号频率范围的中点。 两个叠加的Weaver架构被用来形成架构。 接收机从多通道通信系统中提取基带I和Q信号，而发射机将基带I和Q信号上变频到多通道通信系统。 取决于选择位的韦弗架构可以增强图像信号并减少所需信号，或者可以在所需信号增强的同时降低图像信号。 由于图像和信号分量从RF LO对称地移位，因此需要较少的IF LO频率或合成器来操作系统。

公开(公告)号：US09143204B2

公开(公告)日：2015-09-22

申请号：US13163562

申请日：2011-06-17

Applicant: KhongMeng Tham ,  Zaw Soe

Inventor： KhongMeng Tham ,  Zaw Soe

IPC: H03G3/10 ,  H04B5/00 ,  G05F3/16

CPC classification number: H03K3/012 ,  G05F3/16 ,  H01Q1/50 ,  H03K17/56 ,  H04B5/0075

Abstract: This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

Abstract translation: 当设计高频（〜60GHz）电路时，本发明消除了对“电容器耦合”或“变压器耦合”的需求以及与这些耦合技术相关联的不期望的寄生电容和电感。 在这个频率下，两个相邻阶段之间的距离需要最小化。 与电源或接地引线串联的谐振电路用于将偏置信号与高频信号隔离开来。 该谐振电路的引入允许使用金属迹线将第一级“直接耦合”到下一级。 “直接耦合”技术将高频信号和偏置电压都通过下一级。 与“交流耦合”或“变压器耦合”方法相比，“直接耦合”方法克服了大的管芯面积使用，因为既不需要电容器也不需要变压器来在级之间传输高频信号。

公开(公告)号：US08487695B2

公开(公告)日：2013-07-16

申请号：US13243880

申请日：2011-09-23

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H03F3/45

CPC classification number: H03H11/1217 ,  H03F3/195 ,  H03F3/301 ,  H03F3/45179 ,  H03F3/505 ,  H03F2203/45528 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03H3/00

Abstract: A differential amplifier comprising a first upper device and a first lower device series coupled between two power supplies and a second upper device and a second lower device series coupled between the two power supplies. A first DC voltage enables the first upper device and the second upper device and a second DC voltage regulates current flow in the first lower device and the second lower device. An AC signal component is coupled to the first upper device and the second lower device while the AC signal complement is coupled to the first lower device and the second upper device. A first output signal between the first upper device and the first lower device. Separate RC networks couple the AC signals to their respective device. A first and second output signal forms between the upper device and the lower device, respectively. All the devices are same channel type.

Abstract translation: 一种差分放大器，包括耦合在两个电源之间的第一上部装置和第一下部装置系列，以及耦合在两个电源之间的第二上部装置和第二下部装置。 第一直流电压使得第一上部装置和第二上部装置能够和第二直流电压调节第一下部装置和第二下部装置中的电流。 当AC信号补码耦合到第一下部装置和第二上部装置时，AC信号分量耦合到第一上部装置和第二下部装置。 第一上部装置和第一下部装置之间的第一输出信号。 单独的RC网络将AC信号耦合到其相应的设备。 分别在上部装置和下部装置之间形成第一和第二输出信号。 所有设备的通道类型相同。

公开(公告)号：US20130143511A1

公开(公告)日：2013-06-06

申请号：US13312806

申请日：2011-12-06

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H04B1/16

CPC classification number: H03F1/42 ,  H03D7/125 ,  H03D7/1441 ,  H03D7/1466 ,  H03D7/165 ,  H03F1/223 ,  H03F3/193 ,  H03F3/387 ,  H03F3/45071 ,  H03F3/45179 ,  H03F2200/108 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H03F2200/72 ,  H03F2200/75 ,  H04L27/38

Abstract: A cascode common source and common gate LNAs operating at 60 GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra.

Abstract translation: 引入并描述了以60GHz操作的共源共栅和公共栅极LNA。 对共源共栅源LNA进行模拟，以达到上部器件宽度与较低器件宽度的最佳比例。 共源共栅源LNA的电压输出转换为电流以馈送并将能量施加到混频器级。 这些输入电流信号将与电流相关联的能量直接施加到混频器中的开关电容器中，以最小化系统的总功耗。 LNA电容耦合到I和Q混频器中的混频器开关，并由正交振荡器产生的时钟使能和禁止。 然后，这些信号被差分放大器放大以产生和和差频谱。

公开(公告)号：US20130141178A1

公开(公告)日：2013-06-06

申请号：US13312820

申请日：2011-12-06

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B19/14 ,  H03B2200/0074

Abstract: Injection locked dividers provide a divided clock signal after being driven by a injected clock signal that is a multiple of the divided clock signal. At injected clock signal at 60 GHz generates a differential 30 GHz clock signal. One innovative construction of the injection locked oscillator reduces the internal capacitive at a node by associating the parasitic capacitance at this node with the inductors of the tapped inductor resonant circuit. This provides more energy flow in the injection pulses applied to the legs of the injection locked circuit providing an increase locking range.

Abstract translation: 注入锁定分频器在被分配的时钟信号的倍数的注入时钟信号驱动之后提供分频时钟信号。 在60 GHz的注入时钟信号产生差分30 GHz时钟信号。 注入锁定振荡器的一个创新结构通过将该节点处的寄生电容与抽头电感谐振电路的电感相关联来减少节点处的内部电容。 这提供了施加到注射锁定电路的腿部的注射脉冲中提供更多的能量流，从而提供增加的锁定范围。

公开(公告)号：US20190214953A1

公开(公告)日：2019-07-11

申请号：US16352575

申请日：2019-03-13

Applicant: Zaw Soe ,  Kevin Jing ,  Steve Gao

Inventor： Zaw Soe ,  Kevin Jing ,  Steve Gao

IPC: H03G1/00 ,  H03F3/45 ,  H03H11/12 ,  H03G5/28

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.