公开(公告)号：US10985754B1

公开(公告)日：2021-04-20

申请号：US16884694

申请日：2020-05-27

申请人： DB HiTek Co., Ltd.

发明人： Sang Mok Lee ,  Joon Tae Jang ,  Seung Hoo Kim

IPC分类号： H03K17/687

摘要： An input/output circuit includes a logic unit configured to generate a first signal and a second signal based on data and a first control signal, a driver including a first PMOS transistor having a first gate, a first source that receives a first voltage from a first voltage source, and a first drain, and a first NMOS transistor having a second gate that receives the second signal, a second source that receives a second voltage from a second voltage source less than the first voltage, and a second drain connected to the first drain, a gate-tracking circuit configured to receive the first signal and transfer the received first signal to the first gate of the first PMOS transistor based on a second control signal, and an input/output terminal connected to the first drain and the second drain.

公开(公告)号：US10910493B2

公开(公告)日：2021-02-02

申请号：US16255118

申请日：2019-01-23

申请人： DB HITEK CO., LTD.

发明人： Choul Joo Ko

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08

摘要： A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a first body region disposed in a substrate and having a first conductivity type, a second body region disposed on the first body region and having the first conductivity type and a portion protruding in a channel length direction, a source region disposed in the second body region and having a second conductivity type, a drain region spaced apart from the protruding portion of the second body region in the channel length direction and having the second conductivity type, a well region configured to electrically connect the protruding portion of the second body region and the drain region and having the second conductivity type, and a gate structure disposed on the protruding portion of the second body region.

公开(公告)号：US20210028307A1

公开(公告)日：2021-01-28

申请号：US16924737

申请日：2020-07-09

申请人： DB HiTek Co., Ltd.

发明人： Joo-Hyung KIM

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/762 ,  H01L21/765 ,  H01L29/66

摘要： A lateral double diffused metal oxide semiconductor (LDMOS) transistor and a semiconductor can reduce the size of the entire power block and can decrease costs by preventing formation of an edge termination region between adjacent device tips or ends along a width direction when the corresponding LDMOS transistor cell has a limited width and the LDMOS transistor a multi-finger LDMOS transistor.

公开(公告)号：US10763358B2

公开(公告)日：2020-09-01

申请号：US16215017

申请日：2018-12-10

申请人： DB HiTek Co., Ltd.

发明人： Jong Ho Lee

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/45

摘要： Disclosed is a high voltage semiconductor device and a method of manufacturing the same.

公开(公告)号：US10749133B2

公开(公告)日：2020-08-18

申请号：US16216241

申请日：2018-12-11

申请人： DB HITEK CO., LTD.

发明人： Sang Woo Nam

IPC分类号： H01L51/52 ,  H01L27/32 ,  H01L51/50

摘要： An anode structure of an organic light emitting diode display device, includes an insulating interlayer disposed on a silicon substrate, a first metal layer pattern disposed on the insulating interlayer comprising a first metal to be configured to upwardly reflect light, a second metal layer pattern formed on the first metal layer pattern comprising a second metal having a work function of 4.0 eV or more, and a diffusion barrier layer pattern interposed between the first metal layer pattern and the second metal layer pattern for preventing elements of the first metal or the second metal from diffusing between the first metal layer and the second metal layer.

公开(公告)号：US20200235144A1

公开(公告)日：2020-07-23

申请号：US16748341

申请日：2020-01-21

申请人： DB HITEK CO., LTD.

发明人： Chang Hun Han ,  In Guen Yeo ,  Jong Man Kim ,  Seong Jin Kim

IPC分类号： H01L27/146

摘要： A backside illuminated image sensor includes a substrate having a frontside surface, a backside surface and a recess formed in a backside surface portion thereof, pixel regions disposed in the substrate, an insulating layer disposed on the frontside surface of the substrate, a bonding pad disposed on a frontside surface of the insulating layer, an anti-reflective layer disposed on the backside surface of the substrate, and a second bonding pad disposed in the recess and electrically connected with the bonding pad. The anti-reflective layer includes a metal oxide layer disposed on the backside surface of the substrate, a first silicon insulating layer disposed on the metal oxide layer, and a second silicon insulating layer disposed on the first silicon insulating layer. The second silicon insulating layer includes a first portion disposed on an inner side surface of the recess and a second portion disposed on a bottom surface of the recess.

公开(公告)号：US20200098297A1

公开(公告)日：2020-03-26

申请号：US16424232

申请日：2019-05-28

申请人： DB HiTek Co., Ltd

发明人： JUNG HEO ,  Seung Jin YEO ,  Jae Hong KO ,  Hoon Sang RYU ,  Woo Hyoung SEO

IPC分类号： G09G3/20

摘要： A display driver integrated circuit (DDI) includes a level shifter unit configured to convert a level of a control signal to a voltage in a range that equal to or greater than a first voltage and is equal to or less than a second voltage and output a switch control signal, and a voltage generator including a capacitor and a switch that is turned on or off based on or in response to the switch control signal and configured to generate at least one third voltage.

公开(公告)号：US20200043435A1

公开(公告)日：2020-02-06

申请号：US16227618

申请日：2018-12-20

申请人： DB HiTek Co., Ltd

发明人： Ik Hyun KIM

IPC分类号： G09G3/36 ,  H03F3/45

摘要： A half-power buffer amplifier includes an amplification unit including first and second nodes, the amplification unit configured to differentially amplify a differential input signal and to output a differentially amplified output signal, a first output unit including a first buffer unit between a first power source having a first voltage and a second power source having a second voltage, a second buffer unit between the first and second power sources, and a first switch unit between the first and second buffer units, and a second output unit including a third buffer unit between the second power source and a third power source having a third voltage, a fourth buffer unit between the second and third power sources, and a second switch unit between the third and fourth buffer units. Each of the first to third buffer units receives the differentially amplified output signal. The first switch unit is turned on or off based on or in response to a pre-driving control signal.

公开(公告)号：US10544038B2

公开(公告)日：2020-01-28

申请号：US16056840

申请日：2018-08-07

申请人： DB HITEK CO., LTD.

发明人： Dong Chun Park ,  Jong Won Sun

IPC分类号： H01L21/02 ,  B81C1/00 ,  B81B7/00 ,  H04R19/00 ,  H04R19/04

摘要： A MEMS microphone includes a substrate having a cavity, a back plate provided over the substrate and having a plurality of acoustic holes, a diaphragm disposed between the substrate and the back plate, and spaced apart from the substrate and the back plate, a strut located at outer side of the diaphragm, having a lower surface in contact with an upper surface of the substrate and being integrally formed with the upper insulation layer to support the upper insulation layer to space the upper insulation layer from the diaphragm, and a bending prevention member provided on an upper surface of the back plate for preventing the back plate from being bent.

公开(公告)号：US20200020268A1

公开(公告)日：2020-01-16

申请号：US16234313

申请日：2018-12-27

申请人： DB HiTek Co., Ltd.

发明人： Kyoung Tae KIM ,  Seung Jin YEO ,  Mun Gyu KIM ,  Jae Hong KO

IPC分类号： G09G3/20 ,  G09G3/3208

摘要： Disclosed is a gamma correction circuit and method capable of minimizing power consumption by adding third and fourth input amplifiers receiving reference voltages which are identical to voltages to first and second input amplifiers, respectively, and deactivating the first and second input amplifiers during an always on display (AOD) mode. The gamma correction circuit includes a first input amplifier configured to output a maximum voltage when active, a second input amplifier configured to output a minimum voltage when active, a third input amplifier configured to output a highest gamma voltage in response to the first reference voltage, and a fourth input amplifier configured to output a lowest gamma voltage in response to the second reference voltage. The first and second input amplifiers are deactivated when the display driving device operates in the AOD mode.