公开(公告)号：US20040202204A1

公开(公告)日：2004-10-14

申请号：US10833772

申请日：2004-04-27

Applicant: ESS Technology, Inc.

Inventor： Ping Dong ,  Jordan C. Cookman

IPC: H04J003/04

CPC classification number: H04L25/0268 ,  H01F2019/085

Abstract: An electrical isolation barrier for use in a Data Access Arrangement uses a high frequency (HF) transformer 24 to provide isolation. An input signal, which may be analog or digital, is connected to a modulator. The analog output of the modulator is connected to the input of the HF transformer. The output of the HF transformer is connected to the input of a demodulator. Simple amplitude modulation can be used in the modulator to modulate the input signal to the frequency range of operation of the HF transformer. A simple low pass filter may be incorporated in the demodulator to remove harmonic distortion caused by the HF transformer. The output signal of the demodulator is substantially the same as input signal.

Abstract translation: 用于数据访问装置的电隔离屏障使用高频（HF）变压器24来提供隔离。 可以是模拟或数字的输入信号连接到调制器。 调制器的模拟输出连接到HF变压器的输入。 HF变压器的输出端连接到解调器的输入端。 可以在调制器中使用简单的幅度调制来将输入信号调制到HF变压器的工作频率范围。 可以在解调器中并入简单的低通滤波器，以消除由HF变压器引起的谐波失真。 解调器的输出信号与输入信号基本相同。

公开(公告)号：US20040193665A1

公开(公告)日：2004-09-30

申请号：US10453901

申请日：2003-06-02

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: G06F017/10

CPC classification number: H03M7/3004 ,  H03H17/0248 ,  H03M7/3028 ,  H03M7/3042

Abstract: The invention is directed to a bi-quad filter circuit configured with sigma-delta devices that operate as binary rate multipliers (BRMs). Unlike conventional bi-quad filter circuits, the invention provides a bi-quad filter configured with a single-bit BRM. In another embodiment, the invention further provides a bi-quad filter configured with multiple-bit BRMs.

Abstract translation: 本发明涉及一种双向滤波器电路，其配置为以二进制比率乘法器（BRM）操作的Σ-Δ器件。 与传统的双通道滤波器电路不同，本发明提供一种配置有单位BRM的双通道滤波器。 在另一个实施例中，本发明还提供一种配置有多位BRM的双二进制滤波器。

公开(公告)号：US20040145509A1

公开(公告)日：2004-07-29

申请号：US10687300

申请日：2003-10-15

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H03M001/36

CPC classification number: H03M1/0854 ,  H03M1/1235 ,  H03M1/144 ,  H03M1/206 ,  H03M1/367

Abstract: An analog-to-digital converter in which each of a plurality of comparators is, in a successive approximation manner, selectively enabled or disabled and the outputs from those comparators summed together to produce a digital signal therefrom. By weighting and mixing outputs of adjacent comparators in proportions calculated to provide an interpolated output of a virtual comparator between the actual comparators, many such virtual comparators can be created without the need for additional fixed hardware elements in the converter. By doing so, the converter is able to produce a digital output having n bits using only N actual hardware elements for comparing signals, where N