公开(公告)号：US20040189501A1

公开(公告)日：2004-09-30

申请号：US10731885

申请日：2003-12-08

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H03M003/00

CPC classification number: H03M7/3015 ,  H03M3/39 ,  H03M3/50 ,  H03M7/3028

Abstract: A sigma delta circuit is provided having a sigma delta modulator configured to operate according to a first clock signal and a quantizer connected to the sigma delta modulator, where the quantizer is configured to operate according to a second clock signal. In operation, if a small amplitude signal is received by the sigma delta circuit, the circuit is configured to operate at a fixed output frequency. When a large amplitude signal is received, the circuit is configured to adjust to a different frequency to accommodate the larger signal. The second clock signal may be a variable clock signal, where the quantizer operates according to a variable clock signal in order to adjust to different input signals.

Abstract translation: 提供了一个Σ-Δ电路，其具有被配置为根据第一时钟信号和连接到Σ-Δ调制器的量化器进行操作的Σ-Δ调制器，其中量化器被配置为根据第二时钟信号进行操作。 在操作中，如果Σ-Δ电路接收到小振幅信号，则电路被配置为以固定的输出频率工作。 当接收到大振幅信号时，电路被配置成调节到不同的频率以适应较大的信号。 第二时钟信号可以是可变时钟信号，其中量化器根据可变时钟信号进行操作，以便调整到不同的输入信号。

公开(公告)号：US20040212525A1

公开(公告)日：2004-10-28

申请号：US10810314

申请日：2004-03-26

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H03M001/66

CPC classification number: H03M1/0663 ,  H03M1/0614 ,  H03M1/0682 ,  H03M1/66

Abstract: A high quality DAC is provided for a lower cost (including the layout size of the circuit on an audio chip) of high end DACs. The DAC includes a first circuit configured to remove even harmonics from a sigma delta circuit, and a second circuit configured to remove odd harmonics.

Abstract translation: 高端DAC的低成本（包括音频芯片的电路布局尺寸）提供了高质量的DAC。 DAC包括被配置为从Σ-Δ电路去除偶次谐波的第一电路和被配置为去除奇数谐波的第二电路。

公开(公告)号：US20040189397A1

公开(公告)日：2004-09-30

申请号：US10402391

申请日：2003-03-27

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H03F003/68

CPC classification number: H03F3/343 ,  H03F2200/453

Abstract: An electronic device is provided such as an amplifier, for example, having improved gain and transconductance and low output impedance. The device includes a primary amplifier configured to carry an operating load. The primary amplifier includes an input for receiving an input signal, and an output for outputting an output signal, and operates having a variable output, as it carries an operational load. The device further includes a secondary amplifier configured to operate at a fixed operating condition, not burdened by carrying an operational load, and includes a secondary input configured to receive the input signal, wherein the secondary amplifier is configured to define the input voltage. The device is configured to detect a difference in operating current between the primary and secondary. amplifiers, and to compensate for any operational load that may be applied to the primary amplifier during operation.

Abstract translation: 提供了诸如具有改善的增益和跨导和低输出阻抗的放大器的电子器件。 该装置包括被配置为承载操作负载的主放大器。 主放大器包括用于接收输入信号的输入端和用于输出输出信号的输出，并且在其承载操作负载时具有可变输出的操作。 该装置还包括辅助放大器，其被配置为在固定的工作状态下操作，而不承受运行负载的负担，并且包括被配置为接收输入信号的次级输入，其中辅助放大器被配置为限定输入电压。 该设备被配置为检测主要和次要之间的工作电流的差异。 放大器，并补偿在运行期间可能施加到主放大器的任何工作负载。

公开(公告)号：US20030189507A1

公开(公告)日：2003-10-09

申请号：US10118224

申请日：2002-04-05

Applicant: ESS TECHNOLOGY, INC.

Inventor： Andrew Martin Mallinson

IPC: H03M001/36

CPC classification number: H03M1/367

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract translation: 一种差分输入闪存模数转换器，其中连接比较器阵列以比较通过在阻抗网络上施加差分输入信号产生的这种信号的抛物面分布中的参考信号。 优选地，比较器阵列包括至少两个多个比较器，第一多个比较器比较由第一步长分隔的参考节点对，而第二多个比较器比较由第二步长分隔的参考节点对。 甚至更优选地，比较器阵列还包括第三多个比较器，其将由第三步长分隔的参考节点对进行比较，但仅在必要时使转换器的可用比较范围最大化。 根据本发明的闪存转换器从输入提供增加的增益，而不会累积比较器输入电流，并且不牺牲参考信号的实际比较的数量。

公开(公告)号：US20040145421A1

公开(公告)日：2004-07-29

申请号：US10351266

申请日：2003-01-23

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H03L007/00

CPC classification number: H03L7/1806 ,  H03L7/18

Abstract: The invention provides a frequency locked loop and related method that enables the conversion of a signal frequency with improved stability. A frequency locked loop embodying the invention includes an input for receiving an input signal and an output for outputting an output signal having a different frequency than the input. A frequency detector is configured to receive the first factored input from the primary channel and the second factored input from the secondary channel, to calculate the difference between the first factored input and the second factored input and to produce an output based on the difference between the two factored inputs. A voltage controlled oscillator is configured to receive the output from the frequency detector, and to produce an output signal. The voltage controlled oscillator ultimately sets the output frequency based on the output of frequency detector. Unlike conventional frequency locked loops, the frequency detector receives the inputs from binary rate multipliers, which operate independently of whether the input factors require complex reduction; this is, independently of whether M and. N are large and relatively prime the circuit is not burdened with slow correction, since the binary rate multipliers are not dependent on the reducibility of the respective input factors. The invention provides a circuit configuration that operates faster and better that any conventional design and that has no inherent pole in the loop. Furthermore, a circuit configured according to the invention operates independent of whether M and N are relatively large irreducible numbers, such as prime numbers.

Abstract translation: 本发明提供一种频率锁定环路和相关方法，其能够以改进的稳定性转换信号频率。 体现本发明的锁频环包括用于接收输入信号的输入端和用于输出具有与输入频率不同的频率的输出信号的输出。 频率检测器被配置为从主信道和第二因子输入从次信道接收第一因子输入，以计算第一因子输入和第二因子输入之间的差，并且基于第二因子输入 两个因素投入。 压控振荡器被配置为接收来自频率检测器的输出并产生输出信号。 压控振荡器最终根据频率检测器的输出设定输出频率。 与常规频率锁定环不同，频率检测器接收来自二进制速率乘法器的输入，其独立于输入因子是否需要复杂的降低; 这是独立于M和。 由于二进制比例乘法器不依赖于相应的输入因子的可还原性，所以电路不加负载，并且相对较大。 本发明提供了一种电路配置，其更快更好地操作任何常规设计，并且在环路中没有固有的极点。 此外，根据本发明配置的电路独立于M和N是否相对较大的不可约数，例如素数。

公开(公告)号：US20040216007A1

公开(公告)日：2004-10-28

申请号：US10810312

申请日：2004-03-26

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson ,  Simon Jacques Damphousse

IPC: H02H003/05

CPC classification number: H03M3/344 ,  H03M3/358

Abstract: A system and method are provided for compensating for output error in a sigma delta circuit. The system includes an input for receiving an input signal and an output configured to output a output signal. The system further includes a summation component configured to add a first error voltage value, which is derived from an output signal, to an incoming input signal, and a subtraction component configured to subtract a second error voltage value, where the second error voltage value is derived from the adding of a first error voltage value to an incoming input signal.

Abstract translation: 提供了一种系统和方法来补偿Σ-Δ电路中的输出误差。 该系统包括用于接收输入信号的输入端和被配置为输出输出信号的输出。 该系统还包括一个相加分量，其被配置为将从输出信号导出的第一误差电压值添加到输入输入信号，以及减法分量，被配置为减去第二误差电压值，其中第二误差电压值为 从输入输入信号中增加第一误差电压值得出。

公开(公告)号：US20040189390A1

公开(公告)日：2004-09-30

申请号：US10680811

申请日：2003-10-06

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H03F003/45

CPC classification number: H03F3/45094 ,  H03F3/005 ,  H03F2203/45461

Abstract: A device is provided having at least two capacitive elements configured to retain a charge, and an interconnection of active devices between the capacitive elements. The active devices are configured to operate upon a transient charge flow as a current when in operation. The charge flow is partitioned into at least two capacitors according to the input voltage difference acting as a controlling parameter.

Abstract translation: 提供了一种器件，其具有被配置为保持电荷的至少两个电容元件以及在电容元件之间的有源器件的互连。 有源器件被配置为在瞬时充电流动时作为工作时的电流工作。 根据作为控制参数的输入电压差，将电荷流分成至少两个电容器。

公开(公告)号：US20030189508A1

公开(公告)日：2003-10-09

申请号：US10346034

申请日：2003-01-15

Applicant: ESS TECHNOLOGY, INC.

Inventor： Andrew Martin Mallinson

IPC: H03M001/36

CPC classification number: H03M1/367

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

公开(公告)号：US20040233088A1

公开(公告)日：2004-11-25

申请号：US10444813

申请日：2003-05-22

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H03M001/66 ,  H03M003/00

CPC classification number: H03M3/504

Abstract: A circuit is provided having a secondary semi-analog FIR filter connected to a primary filter via a coefficient to reduce the size of the sizes of the resistors used in the primary filter. The coefficient may be one or more intermediate resistors connected between separate resistor/voltage driver banks that make up the FIR filter. The result is a circuit that takes up less chip space required to accommodate the required resistance for a digital to analog converter (DAC). The invention configures the resistor structure to produce the same output result as a conventional circuit, but with smaller resistor values that take up less surface area on the chip.

Abstract translation: 提供具有通过系数连接到初级滤波器的次级半模拟FIR滤波器以减小在初级滤波器中使用的电阻器的尺寸的尺寸的电路。 该系数可以是连接在构成FIR滤波器的分立电阻/电压驱动器组之间的一个或多个中间电阻器。 结果是一个电路占用更少的芯片空间，以适应数模转换器（DAC）所需的电阻。 本发明构造了电阻器结构以产生与常规电路相同的输出结果，但是具有较小的电阻值，其占用较小的芯片表面积。

公开(公告)号：US20040213364A1

公开(公告)日：2004-10-28

申请号：US10810313

申请日：2004-03-26

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H04L027/06

CPC classification number: H03H17/027 ,  H03H2218/06 ,  H04L27/2601

Abstract: A signal processor has a plurality of channels, each channel configured to receive an input signal stream, to reduce the signal to a direct current signal and to process the signal according to the stream signal. Each channel also has a plurality of low pass filters configured to filter in-phase and quadrature-phase modulator outputs with a first low pass filter and to filter a reference quadrature signals, and a gain control configured to re-modulate gain adjusted output signals with the filtered quadrature signals. The processor further includes an inverter to invert the in-phase filtered reference signal and means to multiply the quadrature gain adjusted output signal.

Abstract translation: 信号处理器具有多个通道，每个通道被配置为接收输入信号流，以将信号减小到直流信号，并根据流信号处理信号。 每个通道还具有多个低通滤波器，其被配置为用第一低通滤波器对同相和正交相位调制器输出进行滤波，并对基准正交信号进行滤波;以及增益控制，被配置为重新调制增益调整的输出信号， 滤波后的正交信号。 处理器还包括反相器，用于反相同相滤波的参考信号，以及将正交增益调整的输出信号相乘的装置。