公开(公告)号：US11909413B2

公开(公告)日：2024-02-20

申请号：US17471887

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Atsushi Kawasumi

IPC: H03M1/36 ,  H03M1/20 ,  G11C7/22 ,  G11C7/16

CPC classification number: H03M1/206 ,  G11C7/16 ,  G11C7/22

Abstract: A semiconductor integrated circuit has a digital signal generator that generates a binary signal whose logic transitions at a timing according to a discharge amount of a second wiring which is discharged when multiplication data of first data stored in a memory cell and second data on a first wiring is a first logic; and a transition timing detector that detects a timing at which the logic of the binary signal transitions.

公开(公告)号：US09054732B2

公开(公告)日：2015-06-09

申请号：US14249973

申请日：2014-04-10

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Tomoya Kakamu

IPC: H03M1/38 ,  H03M1/12 ,  H03M1/46 ,  H03M1/44

CPC classification number: H03M1/38 ,  H03M1/129 ,  H03M1/162 ,  H03M1/206 ,  H03M1/44 ,  H03M1/468

Abstract: An SAR analog-to-digital conversion circuit includes: first and second CDACs; first to third comparators respectively comparing outputs of the first and second CDACs, output levels of the first and third CDACs with a reference level; an arithmetic operation circuit; and an SAR control circuit, wherein the SAR control circuit: at each step, determines in which of four ranges output levels of the sampled and held signals of the first and second CDACs are included, the four ranges corresponding to the conversion range being quartered, determines two bits of the digital data and adjusts the output levels of the first and second CDACs so that a level at ¼ or ¾ of the voltage range agrees with the intermediate level, and controls first and second switches so that the voltage range is set to be a conversion range at a next step.

Abstract translation: SAR模数转换电路包括：第一和第二CDAC; 分别比较第一和第二CDAC的输出，第一和第三CDAC的输出电平与参考电平的第一至第三比较器; 算术运算电路; SAR控制电路，其中所述SAR控制电路：在每个步骤中确定在四个范围中的哪一个范围中包括所述第一和第二CDAC的采样和保持的信号的输出电平，与所述转换范围相对应的四个范围被分配， 确定数字数据的两位，并调整第一和第二CDAC的输出电平，使得电压范围的1/4或¾的电平与中间电平一致，并且控制第一和第二开关，使得电压范围被设置为 作为下一步的转换范围。

公开(公告)号：US20120105264A1

公开(公告)日：2012-05-03

申请号：US12981664

申请日：2010-12-30

Applicant: Seung-Tak Ryu ,  Jong-In Kim ,  Ki-Jin Kim ,  Kwang Ho Ahn

Inventor： Seung-Tak Ryu ,  Jong-In Kim ,  Ki-Jin Kim ,  Kwang Ho Ahn

IPC: H03M1/38

CPC classification number: H03M1/002 ,  H03M1/205 ,  H03M1/206 ,  H03M1/365

Abstract: An analog-to-digital converter includes: a first latch row corresponding to a first stage; a second latch row corresponding to a second stage; and a digital processor for encoding output signals of the second latch row and generating a digital signal. The first latch row includes a plurality of first latches that receive an analog input signal and reference voltages and operate in synchronization with a first clock signal, and the second latch row includes: a plurality of second latches that receive outputs signals of the plurality of first latches and operate in synchronization with a second clock signal delayed from the first reference clock; and a plurality of third latches that receive output signals of two neighboring latches of the plurality of first latches and operate in synchronization with the second clock signal by means of an interpolation technique.

Abstract translation: 模数转换器包括：对应于第一级的第一锁存行; 对应于第二级的第二锁存行; 以及用于对第二锁存行的输出信号进行编码并产生数字信号的数字处理器。 第一锁存行包括接收模拟输入信号和参考电压并与第一时钟信号同步操作的多个第一锁存器，并且第二锁存行包括：多个第二锁存器，其接收多个第一锁存器的输出信号 锁存并与从第一参考时钟延迟的第二时钟信号同步操作; 以及多个第三锁存器，其接收所述多个第一锁存器中的两个相邻锁存器的输出信号，并且通过插值技术与所述第二时钟信号同步地操作。

公开(公告)号：US07893855B2

公开(公告)日：2011-02-22

申请号：US12485924

申请日：2009-06-17

Applicant: Sheng-Jui Huang

Inventor： Sheng-Jui Huang

IPC: H03M3/00

CPC classification number: H03F3/45475 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/4565 ,  H03F3/45932 ,  H03F2200/408 ,  H03F2203/45366 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45514 ,  H03F2203/45562 ,  H03F2203/45594 ,  H03F2203/45644 ,  H03H11/1252 ,  H03H11/1291 ,  H03M1/0663 ,  H03M1/0809 ,  H03M1/206 ,  H03M1/361 ,  H03M1/806 ,  H03M3/424 ,  H03M3/448 ,  H03M3/464

Abstract: An exemplary continuous-time delta-sigma analog-to-digital converter includes a loop filter, a quantizer, a dynamic element matching circuit, a latch, and a digital-to-analog converter (DAC). The loop filter contains a plurality of integrators coupled in series, including a first integrator and a second integrator; a first positive feedback resistive element, placed in a first positive feedback path between a first output node of the second integrator and a first input node of the first integrator; and a first negative feedback resistive element, placed in a first negative feedback path between a second output node of the second integrator and a second input node of the first integrator. The quantizer is implemented using a domino quantizer. The DAC contains a plurality of DAC units each having a capacitive device, a resistive device, and a switch device coupled between the capacitive device and the resistive device.

Abstract translation: 示例性连续时间Δ-Σ模数转换器包括环路滤波器，量化器，动态元件匹配电路，锁存器和数模转换器（DAC）。 环路滤波器包括串联耦合的多个积分器，包括第一积分器和第二积分器; 第一正反馈电阻元件，放置在第二积分器的第一输出节点与第一积分器的第一输入节点之间的第一正反馈路径中; 以及第一负反馈电阻元件，放置在第二积分器的第二输出节点与第一积分器的第二输入节点之间的第一负反馈路径中。 量化器使用多米诺量化器实现。 DAC包含多个DAC单元，每个DAC单元均具有电容性器件，电阻器件和耦合在电容器件和电阻器件之间的开关器件。

公开(公告)号：US07855667B2

公开(公告)日：2010-12-21

申请号：US12389122

申请日：2009-02-19

Applicant: Sanroku Tsukamoto

Inventor： Sanroku Tsukamoto

IPC: H03M1/10

CPC classification number: H03M1/1004 ,  H03M1/206 ,  H03M1/365

Abstract: A semiconductor device is described which includes a first comparator judging the level of an input signal based on a first judgment value, a second comparator judging the level of the input signal based on a second judgment value, and a calibrator outputting a control signal for starting the calibration of the second judgment value in the case that the calibration of the first judgment value is ended.

Abstract translation: 描述了一种半导体器件，其包括：第一比较器，其基于第一判断值判定输入信号的电平;第二比较器，基于第二判断值判定输入信号的电平;以及校准器，输出用于启动的控制信号 在第一判断值的校准结束的情况下校正第二判断值。

公开(公告)号：US20100045496A1

公开(公告)日：2010-02-25

申请号：US12389122

申请日：2009-02-19

Applicant: Sanroku TSUKAMOTO

Inventor： Sanroku TSUKAMOTO

IPC: H03M1/10

CPC classification number: H03M1/1004 ,  H03M1/206 ,  H03M1/365

Abstract: A semiconductor device is described which includes a first comparator judging the level of an input signal based on a first judgment value, a second comparator judging the level of the input signal based on a second judgment value, and a calibrator outputting a control signal for starting the calibration of the second judgment value in the case that the calibration of the first judgment value is ended.

Abstract translation: 描述了一种半导体器件，其包括：第一比较器，其基于第一判断值判定输入信号的电平;第二比较器，基于第二判断值判定输入信号的电平;以及校准器，输出用于启动的控制信号 在第一判断值的校准结束的情况下校正第二判断值。

公开(公告)号：US07561092B2

公开(公告)日：2009-07-14

申请号：US12019627

申请日：2008-01-24

Applicant: John Philip Tero

Inventor： John Philip Tero

IPC: H03M1/12 ,  H03M1/34

CPC classification number: H03M1/206 ,  H03M1/361

Abstract: ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an interpolating comparator. The interpolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.

Abstract translation: 通过比较器阵列中的比较器输出的内插，ADC精度增加1位，从而提高精度，而不会显着增加功耗和尺寸。 具体地，模数转换器包括二进制转换器和比较器阵列，其包括多个比较器块，每个块具有主比较器和内插比较器。 内插比较器将来自主比较器的输出信号与来自多个块中另一块的主比较器的负输出信号进行比较，以生成最低有效位。 耦合到阵列的二进制转换器将阵列输出转换为二进制代码。

公开(公告)号：US20090153388A1

公开(公告)日：2009-06-18

申请号：US12270609

申请日：2008-11-13

Applicant: Mikko WALTARI ,  Costantino Pala

Inventor： Mikko WALTARI ,  Costantino Pala

IPC: H03M1/36

CPC classification number: H03M1/206 ,  H03M1/1061 ,  H03M1/362 ,  H03M1/365 ,  H03M1/50

Abstract: An input signal is compared to 2N−1 reference voltages to generate 2N−1 corresponding binary valued comparison signals, delaying at least one of the comparison signals by a variable delay and detecting a difference in arrival time between the delayed signal and another comparison signal. A time interpolation signal encoding a plurality of bins within a least significant bit quantization level is generated, based on the detected difference in arrival time. An M-bit output data is generated based on the comparison signals and the time interpolation signal. A non-uniformity of a code density of the M-bit output data is detected, and based on the detecting the delaying is varied.

Abstract translation: 将输入信号与2N-1个参考电压进行比较以产生2N-1个对应的二进制值比较信号，延迟比较信号中的至少一个可变延迟并检测延迟信号与另一个比较信号之间的到达时间差。 基于检测到的到达时间的差异，生成对最低有效位量化级内的多个存储体进行编码的时间插值信号。 基于比较信号和时间插值信号生成M位输出数据。 检测到M位输出数据的密度不均匀，并且基于检测延迟变化。

公开(公告)号：US20060087455A1

公开(公告)日：2006-04-27

申请号：US11254453

申请日：2005-10-20

Applicant: Hao-Feng Hung

Inventor： Hao-Feng Hung

IPC: H03M1/22

CPC classification number: H03M1/206 ,  H03M1/303

Abstract: The invention provides an interpolation apparatus for improving the resolution of an optical encoder. The optical encoder outputs an encoding signal, and the encoding signal corresponds to a first resolution. The interpolation apparatus comprises a comparing circuit and a lookup table circuit. The comparator receives the encoding signal and produces a plurality of comparison signals. The lookup table circuit receives a plurality of comparison signals and produces an outputted signal, wherein the outputted signal corresponds to second resolution. The second resolution is greater than the first resolution.

Abstract translation: 本发明提供一种用于提高光学编码器分辨率的内插装置。 光学编码器输出编码信号，编码信号对应于第一分辨率。 插值装置包括比较电路和查找表电路。 比较器接收编码信号，产生多个比较信号。 查找表电路接收多个比较信号并产生输出信号，其中输出的信号对应于第二分辨率。 第二项决议大于第一项决议。

公开(公告)号：US06914543B2

公开(公告)日：2005-07-05

申请号：US10160862

申请日：2002-06-03

Applicant: John H. Floros ,  Nick Sarafopoulos ,  Paul T. Jordan

Inventor： John H. Floros ,  Nick Sarafopoulos ,  Paul T. Jordan

IPC: G01D5/245 ,  H03M1/20 ,  H03M1/30 ,  H03M1/64 ,  H03M1/22

CPC classification number: H03M1/206 ,  G01D5/2457 ,  H03M1/303 ,  H03M1/308 ,  H03M1/645

Abstract: A method for detecting an absolute rotational position of an electromechanical device or the at least one component thereof comprising determining a first absolute position of the electromechanical device or the at least one component thereof based on a commutation index signal, obtaining a Z-index signal, and determining a second absolute position of the electromechanical device or the at least one component thereof based on the Z-index signal. The method initially determines a coarse rotational position of the electromechanical device such as a rotor or steering wheel based on the commutation index signal. When a device's position is first initialized by a commutation index signal before the Z-index pulse is detected, the device's position is re-initialized upon detection of the Z-Index pulse to provide a more accurate absolute device rotational position.

Abstract translation: 一种用于检测机电装置或其至少一个部件的绝对旋转位置的方法，包括基于换向指数信号确定机电装置或其至少一个部件的第一绝对位置，获得Z指数信号， 以及基于所述Z-索引信号确定所述机电装置或其所述至少一个部件的第二绝对位置。 该方法最初基于换向指数信号确定诸如转子或方向盘的机电装置的粗略旋转位置。 当在检测到Z-索引脉冲之前首先用换向索引信号来初始化设备的位置时，在检测到Z-索引脉冲之后重新初始化设备的位置以提供更准确的绝对设备旋转位置。