公开(公告)号：US20150022111A1

公开(公告)日：2015-01-22

申请号：US14330390

申请日：2014-07-14

Applicant: Generalplus Technology Inc.

Inventor： Yu-Chung CHANG

IPC: H05B33/08

CPC classification number: H05B33/0815 ,  G01R31/3187 ,  H05B33/0803 ,  H05B33/089

Abstract: An LED device with built-in fast self-test circuit includes at least one LED unit, a data shift and latch register, a control unit, at least one multiplexer, and an LED driver unit. The data shift and latch register receives a serial data signal. The control unit receives the serial data signal to detect whether there is normal data transmission based on the serial data signal. When there is no data transmission, the control unit enables a multiplex control signal. The multiplexer is connected to the control unit and the data shift and latch register. According to the multiplex control signal, the multiplexer selects the control unit or the data shift and latch register as an output. The LED driver unit is connected to at least one LED unit and the multiplexer to drive the LED unit based on the output of the multiplexer.

Abstract translation: 具有内置快速自检电路的LED装置包括至少一个LED单元，数据移位和锁存寄存器，控制单元，至少一个多路复用器和LED驱动单元。 数据移位和锁存寄存器接收串行数据信号。 控制单元接收串行数据信号，以基于串行数据信号检测是否存在正常的数据传输。 当没有数据传输时，控制单元启用复用控制信号。 多路复用器连接到控制单元和数据移位寄存器和锁存寄存器。 根据复用控制信号，多路复用器选择控制单元或数据移位和锁存寄存器作为输出。 LED驱动器单元连接到至少一个LED单元和多路复用器，以基于多路复用器的输出来驱动LED单元。

公开(公告)号：US20140368284A1

公开(公告)日：2014-12-18

申请号：US14166637

申请日：2014-01-28

Applicant: Generalplus Technology Inc.

Inventor： Shih-Ming LUO ,  Min LU

IPC: H03K3/36

CPC classification number: H03K3/0231 ,  H03K3/03 ,  H03K4/501

Abstract: A relaxation oscillator is provided in the present invention. The relaxation oscillator includes a R-S latch, a first delay circuit and a second delay circuit. The input terminal of the first delay circuit is coupled to the Q output terminal of the R-S latch, and the output terminal of the first delay circuit is coupled to the reset terminal of the R-S latch. The input terminal of the second delay circuit is coupled to the inversion Q output terminal of the R-S latch, and the output terminal of the second delay circuit is coupled to the set terminal of the R-S latch. When the input terminal of the first delay circuit inputs a first logic voltage, after a delay time, the output terminal of the first delay circuit outputs a second logic pulse. When the input terminal of the second delay circuit inputs the first logic voltage, after the delay time, the output terminal of the second delay circuit outputs the second logic pulse.

Abstract translation: 在本发明中提供了张弛振荡器。 张弛振荡器包括R-S锁存器，第一延迟电路和第二延迟电路。 第一延迟电路的输入端耦合到R-S锁存器的Q输出端，第一延迟电路的输出端耦合到R-S锁存器的复位端。 第二延迟电路的输入端耦合到R-S锁存器的反相Q输出端，第二延迟电路的输出端耦合到R-S锁存器的设定端。 当第一延迟电路的输入端输入第一逻辑电压时，在延迟时间之后，第一延迟电路的输出端输出第二逻辑脉冲。 当第二延迟电路的输入端输入第一逻辑电压时，在延迟时间之后，第二延迟电路的输出端输出第二逻辑脉冲。

公开(公告)号：US20140240099A1

公开(公告)日：2014-08-28

申请号：US14043236

申请日：2013-10-01

Applicant: Generalplus Technology Inc.

Inventor： Down Xu CHUANG

IPC: G06K7/10 ,  H02J17/00

CPC classification number: H02J50/12 ,  G06K19/0703 ,  H02J17/00

Abstract: A circuit for signal decoding in RFID or wireless power charging is provided in the present invention. The implement of the present invention is to add a current sense resistor connected to an upper switch or a lower switch the up arm switch or low arm switch to decode the signal on the current sense resistor. Since the error would occur in the original voltage decoder of the wireless power or RFID when the load is heavy and voltage signal swing is large, such that the charge status and then the off-line status cyclically occur and then the charge status . . . occurs in cycle when the mobile device is charging under charge. Since the present invention uses the voltage and current for decoding at the same time, the decoding would be succeed whenever the load is light or heavy.

Abstract translation: 本发明提供了RFID或无线电力充电中的信号解码电路。 本发明的实施例是将连接到上开关或下开关的电流检测电阻器添加到上臂开关或低臂开关以对电流检测电阻器上的信号进行解码。 由于当负载很重并且电压信号摆幅较大时，无线电源或RFID的原始电压解码器将发生错误，从而使充电状态和离线状态循环发生，然后再充电状态。 。 。 当移动设备正在充电时发生在循环中。 由于本发明同时使用电压和电流进行解码，每当负载轻或重时，解码将成功。

公开(公告)号：US20140215432A1

公开(公告)日：2014-07-31

申请号：US14160047

申请日：2014-01-21

Applicant: GENERALPLUS TECHNOLOGY INC.

Inventor： YEN TSUN HUANG

IPC: G06F9/44

CPC classification number: G06F8/54 ,  G06F8/447

Abstract: A code generating system includes a code converting module and a linker. The code converting module is configured to generate a plurality of candidate instructions, in response to a source code. The candidate instructions are then saved in an object file. The linker comprises a selecting unit which is configured to select at least one instruction, in response to a sub-hardware condition of a hardware condition, from the plurality of candidate instructions. Moreover, the linker is configured to link the selected at least one instruction to generate a final code.

Abstract translation: 代码生成系统包括代码转换模块和链接器。 代码转换模块被配置为响应于源代码生成多个候选指令。 然后将候选指令保存在目标文件中。 链接器包括选择单元，其被配置为响应于硬件条件的子硬件状况从多个候选指令中选择至少一个指令。 此外，链接器被配置为链接所选择的至少一个指令以生成最终代码。

公开(公告)号：US20130293399A1

公开(公告)日：2013-11-07

申请号：US13855030

申请日：2013-04-02

Applicant: GENERALPLUS TECHNOLOGY INC.

Inventor： Tung-Tsai LIAO ,  Hsin-Chou LEE ,  Hsin-Lung LAI

IPC: H03M11/20

CPC classification number: H03M11/20 ,  H03M11/08

Abstract: An ultra-low power wakeup circuit device includes a keyboard, a key scan circuit, a storage unit, and a comparator unit. The key scan circuit sequentially outputs scanning signals from the first scan line to N-th scan line for acquiring N key scan data. The key scan circuit performs an XOR operation on the N key scan data to generate a current key scan data. The storage unit is connected to the key scan circuit for receiving the current key scan data and storing the current key scan data as a previous key scan data. The comparator unit is connected to the key scan circuit and the storage unit for comparing the current key scan data with the previous key scan data.When the current key scan data is different from the previous key scan data, the comparator unit generates a wakeup signal.

Abstract translation: 超低功率唤醒电路装置包括键盘，键扫描电路，存储单元和比较器单元。 按键扫描电路顺序输出从第一扫描线到第N扫描线的扫描信号，以获取N个键扫描数据。 键扫描电路对N键扫描数据执行XOR操作，以生成当前键扫描数据。 存储单元连接到键扫描电路，用于接收当前键扫描数据并将当前键扫描数据存储为先前的键扫描数据。 比较器单元连接到键扫描电路和存储单元，用于将当前键扫描数据与先前的键扫描数据进行比较。 当当前的键扫描数据与先前的键扫描数据不同时，比较器单元产生唤醒信号。