公开(公告)号：US20080201550A1

公开(公告)日：2008-08-21

申请号：US12111940

申请日：2008-04-29

申请人： David Alan Bailey ,  William Joseph Armstrong ,  Naresh Nayar ,  Gregory Michael Nordstrom

发明人： David Alan Bailey ,  William Joseph Armstrong ,  Naresh Nayar ,  Gregory Michael Nordstrom

IPC分类号： G06F12/06

CPC分类号： G06F9/5077

摘要： A partition manager includes an I/O reconfiguration mechanism and a logical partition suspend/resume mechanism that work together to perform autonomic I/O reconfiguration in a logically partitioned computer system. When I/O reconfiguration is required, the affected logical partitions are suspended, the I/O is reconfigured, and the affected logical partitions are resumed. Because the logical partitions are suspended during I/O reconfiguration, any ghost packet that may occur when the I/O is reconfigured is ignored.

摘要翻译： 分区管理器包括I / O重新配置机制和逻辑分区挂起/恢复机制，其协同工作以在逻辑分区的计算机系统中执行自主I / O重新配置。 当需要I / O重新配置时，受影响的逻辑分区将被挂起，重新配置I / O，并恢复受影响的逻辑分区。 因为逻辑分区在I / O重新配置期间被挂起，所以当I / O被重新配置时可能发生的任何ghost数据包被忽略。

公开(公告)号：US07389400B2

公开(公告)日：2008-06-17

申请号：US11304136

申请日：2005-12-15

申请人： Michael J. Corrigan ,  Paul LuVerne Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward John Silha

发明人： Michael J. Corrigan ,  Paul LuVerne Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward John Silha

IPC分类号： G06F12/00

CPC分类号： G06F12/1036 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/683

摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.

摘要翻译： 一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。 在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。 可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。 在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。 在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。 以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而地址转换高速缓存中的其他条目是无效的。

公开(公告)号：US07281075B2

公开(公告)日：2007-10-09

申请号：US10422513

申请日：2003-04-24

申请人： William Joseph Armstrong ,  David Anthony Larson ,  Naresh Nayar

发明人： William Joseph Armstrong ,  David Anthony Larson ,  Naresh Nayar

IPC分类号： G06F13/24

CPC分类号： G06F9/45533 ,  G06F13/24

摘要： A method, system, and article of manufacture for processing virtual interrupts in a logically partitioned system are provided. An intelligent virtual global interrupt queue (virtual GIQ) that may be associated with a plurality of virtual processors running in a logical partition may be utilized. Upon receiving a virtual interrupt, the virtual GIQ may examine the operating states of the associated virtual processors. In an effort to ensure the virtual interrupt is processed as quickly as possible, the virtual GIQ may present the virtual interrupt to one of the associated virtual processors determined to be in an operating state best suited for processing the virtual interrupt.

摘要翻译： 提供了一种用于处理逻辑分区系统中的虚拟中断的方法，系统和制品。 可以利用可以与在逻辑分区中运行的多个虚拟处理器相关联的智能虚拟全局中断队列（虚拟GIQ）。 在接收到虚拟中断时，虚拟GIQ可以检查相关联的虚拟处理器的操作状态。 为了确保尽可能快地处理虚拟中断，虚拟GIQ可以将虚拟中断呈现给被确定为处于最适合于处理虚拟中断的操作状态的相关虚拟处理器之一。

公开(公告)号：US20060242442A1

公开(公告)日：2006-10-26

申请号：US11110180

申请日：2005-04-20

申请人： William Armstrong ,  Michael Corrigan ,  Naresh Nayar ,  Scott Swaney

发明人： William Armstrong ,  Michael Corrigan ,  Naresh Nayar ,  Scott Swaney

IPC分类号： G06F1/12

CPC分类号： G06F1/14

摘要： A method, apparatus, and computer program product are disclosed in a data processing system for providing a virtualized time base in a logically partitioned data processing system. A time base is determined for each one of multiple processor cores. The time base is used to indicate a current time to one of the processor cores for which the time base is determined. The time bases are synchronized together for the processor cores such that each one of the processor cores includes its own copy of a synchronized time base. For one of the processor cores, a virtualized time base is generated that is different from the synchronized time base but that remains synchronized with at least a portion of the synchronized time base. The processor core utilizes the virtualized time base instead of the synchronized time base for indicating the current time to the processor core. The synchronized time bases and the portion of the virtualized time base remaining in synchronization together.

公开(公告)号：US07000051B2

公开(公告)日：2006-02-14

申请号：US10403158

申请日：2003-03-31

申请人： William Joseph Armstrong ,  Richard Louis Arndt ,  Naresh Nayar

发明人： William Joseph Armstrong ,  Richard Louis Arndt ,  Naresh Nayar

IPC分类号： G06F13/24 ,  G06F9/45

CPC分类号： G06F13/24 ,  G06F9/45541 ,  G06F9/4812 ,  G06F9/5077

摘要： A resource and partition manager virtualizes interrupts without using any additional hardware in a way that does not disturb the interrupt processing model of operating systems running on a logical partition. In other words, the resource and partition manager supports virtual interrupts in a logically partitioned computer system that may include share processors with no changes to a logical partition's operating system. A set of virtual interrupt registers is created for each virtual processor in the system. The resource and partition manager uses the virtual interrupt registers to process interrupts for the corresponding virtual processor. In this manner, from the point of view of the operating system, the interrupt processing when the operating system is running in a logical partition that may contain shared processors and virtual interrupts is no different that the interrupt processing when the operating system is running in computer system that only contains dedicated processor partitions.

摘要翻译： 资源和分区管理器以不干扰在逻辑分区上运行的操作系统的中断处理模型的方式，虚拟化中断而不使用任何附加硬件。 换句话说，资源和分区管理器支持逻辑分区的计算机系统中的虚拟中断，其可以包括共享处理器，而不改变逻辑分区的操作系统。 为系统中的每个虚拟处理器创建一组虚拟中断寄存器。 资源和分区管理器使用虚拟中断寄存器来处理相应虚拟处理器的中断。 以这种方式，从操作系统的观点来看，当操作系统在可能包含共享处理器和虚拟中断的逻辑分区中运行时的中断处理与操作系统在计算机中运行时的中断处理没有区别 只包含专用处理器分区的系统。

公开(公告)号：US20050027960A1

公开(公告)日：2005-02-03

申请号：US10631535

申请日：2003-07-31

申请人： Jonathan DeMent ,  Cathy May ,  Naresh Nayar ,  Edward Silha

发明人： Jonathan DeMent ,  Cathy May ,  Naresh Nayar ,  Edward Silha

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1036 ,  G06F2212/152

摘要： The present invention provides for storing and using a stored logical partition indicia in a TLB. A partition in a microprocessor architecture is employed. A virtual page number is selected. A stored LPID indicia corresponding to the selected page number is read from a TLB. The stored logical partition indicia from the TLB is compared to a logical partition indicia associated with the employed partition. If the stored logical partition indicia and the logical partition indicia associated with the employed partition match, a corresponding page table entry stored in the translation look-aside buffer is read. If they do not match, a page table entry from a page table entry source is retrieved and stored in the TLB. If a partition is to invalidate an entry in the TLB, a TLB entry command is generated and used to invalidate a memory entry.

摘要翻译： 本发明提供了在TLB中存储和使用存储的逻辑分区标记。 采用微处理器架构中的分区。 选择虚拟页码。 从TLB中读取对应于所选页码的存储的LPID标记。 将来自TLB的存储的逻辑分区标记与与所使用的分区相关联的逻辑分区标记进行比较。 如果所存储的逻辑分区标记和与所采用分区相关联的逻辑分区标记匹配，则读取存储在转换后备缓冲器中的相应页表条目。 如果它们不匹配，则从页表入口源中的页表项被检索并存储在TLB中。 如果分区要使TLB中的条目无效，则会生成TLB条目命令，并将其用于使内存条目无效。

公开(公告)号：US20050021936A1

公开(公告)日：2005-01-27

申请号：US10624808

申请日：2003-07-22

申请人： David Bailey ,  William Armstrong ,  Naresh Nayar ,  Gregory Nordstrom

发明人： David Bailey ,  William Armstrong ,  Naresh Nayar ,  Gregory Nordstrom

IPC分类号： G06F9/00

CPC分类号： G06F9/5077

摘要： A partition manager includes an I/O reconfiguration mechanism and a logical partition suspend/resume mechanism that work together to perform autonomic I/O reconfiguration in a logically partitioned computer system. When I/O reconfiguration is required, the affected logical partitions are suspended, the I/O is reconfigured, and the affected logical partitions are resumed. Because the logical partitions are suspended during I/O reconfiguration, any ghost packet that may occur when the I/O is reconfigured is ignored.

摘要翻译： 分区管理器包括I / O重新配置机制和逻辑分区挂起/恢复机制，其协同工作以在逻辑分区的计算机系统中执行自主I / O重新配置。 当需要I / O重新配置时，受影响的逻辑分区将被挂起，重新配置I / O，并恢复受影响的逻辑分区。 因为逻辑分区在I / O重新配置期间被挂起，所以当I / O被重新配置时可能发生的任何ghost数据包被忽略。

公开(公告)号：US09027021B2

公开(公告)日：2015-05-05

申请号：US13445051

申请日：2012-04-12

申请人： Richard L. Arndt ,  Naresh Nayar ,  Christopher Francois ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Randal C. Swanberg

发明人： Richard L. Arndt ,  Naresh Nayar ,  Christopher Francois ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Randal C. Swanberg

IPC分类号： G06F9/455 ,  G06F1/00

CPC分类号： G06F9/45533 ,  G06F9/45541 ,  G06F2009/45575

摘要： A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.

摘要翻译： 在逻辑分区的数据处理系统中提供一种机制，用于控制虚拟处理器的空闲状态的退出的深度和等待时间。 一个虚拟化层产生一个雪松延迟设置信息（CLSI）数据。 响应于引导逻辑分区，虚拟化层将CLSI数据传送到逻辑分区的操作系统（OS）。 OS根据CLSI数据确定在OS控制下的虚拟处理器的特定空闲状态。 响应于调用虚拟化层的OS，OS将虚拟处理器的特定空闲状态传送到虚拟化层，以将特定的空闲状态和唤醒特性分配给虚拟处理器。

公开(公告)号：US20130179892A1

公开(公告)日：2013-07-11

申请号：US13345002

申请日：2012-01-06

申请人： Giles R. Frazier ,  Bruce Mealy ,  Naresh Nayar

发明人： Giles R. Frazier ,  Bruce Mealy ,  Naresh Nayar

IPC分类号： G06F9/46 ,  G06F13/24

CPC分类号： G06F21/6218 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/45541 ,  G06F9/45558 ,  G06F2009/45587

摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

公开(公告)号：US08407515B2

公开(公告)日：2013-03-26

申请号：US12115625

申请日：2008-05-06

申请人： Peter Joseph Heyrman ,  Naresh Nayar ,  Gary Ross Ricard

发明人： Peter Joseph Heyrman ,  Naresh Nayar ,  Gary Ross Ricard

IPC分类号： G06F11/00

CPC分类号： G06F11/2082 ,  G06F11/2094

摘要： A method and apparatus for transparently handling recurring correctable errors and uncorrectable errors in a mirrored memory system prevents costly system shutdowns for correctable memory errors or system failures from uncorrectable memory errors. When a high number of correctable errors are detected for a given memory location, a memory relocation mechanism in the hypervisor moves the data associated with the memory location to an alternate physical memory location transparently to the partition such that the partition has no knowledge that the physical memory actualizing the memory location has been changed. When a correctable error occurs, the memory relocation mechanism uses data from a partner mirrored memory block as a data source for the memory block with the uncorrectable error and then relocates the data to a newly allocated memory block to replace the memory block with the uncorrectable error.

摘要翻译： 用于透明地处理镜像存储器系统中的可重复校正错误和不可校正错误的方法和装置防止由于不可校正的存储器错误而导致的可校正存储器错误或系统故障的昂贵的系统关闭。 当对于给定的存储器位置检测到大量的可校正错误时，管理程序中的存储器重定位机制将与存储器位置相关联的数据透明地移动到备用物理存储器位置到分区，使得分区不知道物理 内存实现内存位置已更改。 当发生可纠正错误时，内存重定位机制使用来自伙伴镜像内存块的数据作为具有不可校正错误的存储器块的数据源，然后将数据重新定位到新分配的存储器块以用不可校正的错误来替换存储器块 。