公开(公告)号：US07429897B1

公开(公告)日：2008-09-30

申请号：US11514489

申请日：2006-08-31

Applicant: Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong

Inventor： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong

IPC: H03B5/08

CPC classification number: H03K3/0315 ,  H03K5/133 ,  H03K2005/00202 ,  H03L7/0995 ,  H03L2207/06

Abstract: Voltage controlled oscillator (VCO) circuitry with low phase noise and a wide range of operating frequencies is presented. The VCO circuitry includes circuitry with two or more VCO sub-circuits, each sub-circuit being optimized to produce output clock signals with low phase noise and with frequencies in a different range. Sub-circuits with gear inputs may be operative to produce output clock signals in a lower range of frequencies, while sub-circuits optimized for high speed operation may be used to produce output signals in a higher range of frequencies. A control circuit may be used to produce a control signal coupled to all sub-circuits. The control signal may set the operating frequency of the sub-circuits.

Abstract translation: 介绍了具有低相位噪声和宽范围工作频率的压控振荡器（VCO）电路。 VCO电路包括具有两个或多个VCO子电路的电路，每个子电路被优化以产生具有低相位噪声和频率在不同范围内的输出时钟信号。 具有齿轮输入的子电路可以用于产生在较低频率范围内的输出时钟信号，而针对高速操作优化的子电路可用于产生较高频率范围内的输出信号。 控制电路可用于产生耦合到所有子电路的控制信号。 控制信号可以设定子电路的工作频率。

公开(公告)号：US07276936B1

公开(公告)日：2007-10-02

申请号：US11239702

申请日：2005-09-29

Applicant: Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  In Whan Kim ,  Thungoc Tran

Inventor： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  In Whan Kim ,  Thungoc Tran

IPC: H03K19/00

CPC classification number: H03K19/1774 ,  H03K19/17744

Abstract: A programmable logic device includes high-speed serial interface (“HSSI”) circuitry that employs one or more clock signals. In addition to use of these clock signals in the HSSI circuitry, circuitry is provided for allowing at least one of these signals to be distributed throughout the PLD core circuitry, e.g., for use as an additional clock signal in the PLD core. Clock distribution is preferably done in a low-skew way.

Abstract translation: 可编程逻辑器件包括采用一个或多个时钟信号的高速串行接口（“HSSI”）电路。 除了在HSSI电路中使用这些时钟信号之外，提供电路以允许这些信号中的至少一个分布在整个PLD核心电路中，例如用作PLD核心中的附加时钟信号。 时钟分布优选以低偏斜方式进行。