公开(公告)号：US09111596B2

公开(公告)日：2015-08-18

申请号：US13967908

申请日：2013-08-15

Applicant: ARM Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Wang-Kun Chen ,  Gus Yeung

IPC: G11C7/10 ,  G11C8/08 ,  G11C8/06

CPC classification number: G11C8/08 ,  G11C7/10 ,  G11C8/06

Abstract: A memory device comprises an array of bitcells arranged as a plurality of rows of bitcells and a plurality of columns of bitcells, and has a plurality of wordlines and a plurality of readout channels. A control unit is configured to control access to the array of bitcells, wherein in response to a memory access request specifying a memory address the control unit is configured to activate a selected wordline and to activate the plurality of readout channels, and to access a row of bitcells in said array storing a data word and addressed by the memory address. The data word consists of a number of data bits given by a number of bitcells in each row of bitcells. The control unit is further configured to be responsive to a masking signal and, when the masking signal is asserted when said memory access request is received, the control unit is configured to activate only a portion of the selected wordline and a portion of the plurality of readout channels, such that only a portion of the data word is accessed.

Abstract translation: 存储器件包括排列成多行比特单元和多列比特单元的位单元阵列，并且具有多个字线和多个读出通道。 控制单元被配置为控制对位单元阵列的访问，其中响应于指定存储器地址的存储器访问请求，控制单元被配置为激活所选择的字线并激活多个读出通道，并且访问行 所述阵列中的位单元存储数据字并由存储器地址寻址。 数据字由每行位单元中的多个位单元给出的多个数据位组成。 所述控制单元还被配置为响应于屏蔽信号，并且当接收到所述存储器访问请求时屏蔽信号被断言时，所述控制单元被配置为仅激活所选字线的一部分和所述多个 读出通道，使得仅访问数据字的一部分。