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    Pulse stretcher circuitry
    1.
    发明授权
    Pulse stretcher circuitry 有权

    公开(公告)号：US11588477B2

    公开(公告)日：2023-02-21

    申请号：US17128800

    申请日：2020-12-21

    Applicant: Arm Limited

    Inventor： Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Yew Keong Chong ,  Gus Yeung

    IPC: H03K5/06 ,  G06F12/0804

    Abstract: Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.

    Pulse Stretcher Circuitry
    2.
    发明申请
    Pulse Stretcher Circuitry 有权

    公开(公告)号：US20210111711A1

    公开(公告)日：2021-04-15

    申请号：US17128800

    申请日：2020-12-21

    Applicant: Arm Limited

    Inventor： Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Yew Keong Chong ,  Gus Yeung

    IPC: H03K5/06 ,  G06F12/0804

    Abstract: Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.

    Low Power Input Gating
    3.
    发明申请
    Low Power Input Gating 有权
    低功率输入门控

    公开(公告)号：US20160343420A1

    公开(公告)日：2016-11-24

    申请号：US14849902

    申请日：2015-09-10

    Applicant: ARM Limited

    Inventor： Andy Wangkun Chen ,  Gus Yeung ,  Yew Keong Chong

    IPC: G11C8/18 ,  G11C8/06

    CPC classification number: G11C8/18 ,  G11C5/141 ,  G11C8/06

    Abstract: Various implementations described herein are directed to an integrated circuit for implementing low power input gating. In one implementation, the integrated circuit may include a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal. The integrated circuit may include a latch device configured to latch the control input of the memory. The integrated circuit may include a latch enable device coupled between the chip enable device and the latch device. The latch enable device may be configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory.

    Abstract translation: 本文所描述的各种实现涉及用于实现低功率输入门控的集成电路。 在一个实现中，集成电路可以包括芯片使能装置，其被配置为接收和使用时钟输入信号，以基于芯片使能信号切换存储器的控制输入。 集成电路可以包括被配置为锁存存储器的控制输入的锁存装置。 集成电路可以包括耦合在芯片使能装置和锁存装置之间的锁存使能装置。 锁存使能装置可以被配置为从芯片使能装置接收时钟输入信号，并且使用时钟输入信号基于锁存使能信号来对锁存器件进行门控，以便有选择地将时钟输入信号切换到控制输入 的记忆。

    Ternary content addressable memory
    4.
    发明授权
    Ternary content addressable memory 有权
    三进制内容可寻址内存

    公开(公告)号：US08848412B1

    公开(公告)日：2014-09-30

    申请号：US13935710

    申请日：2013-07-05

    Applicant: Arm Limited

    Inventor： Gus Yeung ,  Yew Keong Chong ,  Wang-Kun Chen

    IPC: G11C15/00 ,  G11C11/56 ,  G11C15/04

    CPC classification number: G11C15/00 ,  G11C11/56 ,  G11C15/04

    Abstract: A ternary content addressable memory (TCAM) has at least one TCAM cell comprising first and second memory bitcells for storing first and second bit values representing a cell state comprising one of a first cell state, a second cell state and a mask cell state. The first and second memory bitcells share a pair of bitlines for accessing the first and second bit values. Access control circuitry is provided for triggering, in response to a clock signal, a read or write access to the first memory bitcell during a first portion of a clock cycle and triggering a read access or write access to the second read bitcell during a second portion of the clock cycle.

    Abstract translation: 三元内容可寻址存储器（TCAM）具有至少一个TCAM单元，其包括用于存储表示包括第一单元状态，第二单元状态和掩码单元状态之一的单元状态的第一和第二位值的第一和第二存储器位单元。 第一和第二存储器位单元共享用于访问第一和第二位值的一对位线。 提供访问控制电路，用于在时钟周期的第一部分期间响应于时钟信号触发对第一存储器位单元的读或写访问，并且在第二部分期间触发对第二读位元的读访问或写访问 的时钟周期。

    Memory device and method of operation of such a memory device
    6.
    发明授权
    Memory device and method of operation of such a memory device 有权
    这种存储器件的存储器件和操作方法

    公开(公告)号：US08971133B1

    公开(公告)日：2015-03-03

    申请号：US14037413

    申请日：2013-09-26

    Applicant: ARM Limited

    Inventor： Bo Zheng ,  Jungtae Kwon ,  Gus Yeung ,  Yew Keong Chong

    IPC: G11C7/10 ,  G11C7/22 ,  G11C7/12 ,  G06F17/50

    CPC classification number: G11C7/12 ,  G11C7/1096

    Abstract: A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.

    Abstract translation: 具有连接到核心电压电平的存储器单元阵列的存储器件，以及用于执行写入操作以便将数据写入到多个寻址的存储器单元中的存取电路。 在执行写入操作之前，至少与包含寻址的存储器单元的阵列中的每列相关联的位线被预充电到外围电压电平。 然后，字线驱动器电路被配置为在与包含寻址的存储器单元的阵列的行相关联的字线上的核心电压电平处断言字线信号。 写复用驱动器电路断言多路复用控制信号以写入多路复用电路，然后根据多路复用器控制信号将每个寻址的存储器单元的位线耦合到写入驱动器电路，该多路复用器控制信号标识哪个列包含寻址的存储器单元。

    Computer Implemented System and Method for Generating a Layout of a Cell Defining a Circuit Component
    7.
    发明申请
    Computer Implemented System and Method for Generating a Layout of a Cell Defining a Circuit Component 有权

    公开(公告)号：US20210019463A1

    公开(公告)日：2021-01-21

    申请号：US17062567

    申请日：2020-10-03

    Applicant: Arm Limited

    Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Gus Yeung ,  Marlin Wayne Frederick, JR. ,  Sriram Thyagarajan

    IPC: G06F30/39 ,  G06F30/30 ,  G06F30/398

    Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

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