公开(公告)号：US12066926B2

公开(公告)日：2024-08-20

申请号：US17861084

申请日：2022-07-08

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F2212/1008

Abstract: According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.

公开(公告)号：US20230411351A1

公开(公告)日：2023-12-21

申请号：US17752560

申请日：2022-05-24

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Vivek Asthana ,  Ettore Amirante

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L23/481 ,  H01L2225/06541 ,  H01L21/76898 ,  H01L25/50 ,  H01L23/53228

Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through an input/output circuit of the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings at least partially in an input/output circuitry of the memory macro unit based on the determined dimensions of the memory macro unit.

公开(公告)号：US11557583B2

公开(公告)日：2023-01-17

申请号：US17017551

申请日：2020-09-10

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony

IPC: H01L27/02 ,  H01L27/092 ,  G06F30/3953 ,  G06F30/392 ,  H01L23/48

Abstract: Various implementations described herein refer to a device having logic circuitry with transistors and gate lines. The device may include a backside power network having buried supply rails with at least one buried supply rail having a continuity break. The transistors may be arranged in a cell architecture having an N-well break with the gate lines passing through the N-well break and the continuity break.

公开(公告)号：US20210389934A1

公开(公告)日：2021-12-16

申请号：US16899502

申请日：2020-06-11

Applicant: Arm Limited

Inventor： Mouli Rajaram Chollangi ,  Sriram Thyagarajan ,  Hongwei Zhu ,  Yew Keong Chong ,  Pratik Ghanshambhai Satasia

IPC: G06F8/30 ,  G06F8/38 ,  G06F8/71 ,  G06F16/901

Abstract: Various implementations described herein are directed to a system and methods for memory compiling. For instance, a method may include selecting source corners from a memory compiler configuration and generating a standardized set of memory instances for the selected source corners. Also, the method may include deriving a reduced set of memory instances based on the standardized set of memory instances and building a memory compiler database for a compiler space based on the standardized set of memory instances and the reduced set of memory instances.

公开(公告)号：US20210295898A1

公开(公告)日：2021-09-23

申请号：US16824663

申请日：2020-03-19

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Ettore Amirante

IPC: G11C11/4097 ,  G11C11/4094 ,  G11C11/408 ,  G11C5/02

Abstract: Various implementations described herein are related to a device having a bitcell. The device may include horizontal bitlines coupled to the bitcell. The horizontal bitlines may include multiple first read bitlines disposed in a horizontal direction with respect to the bitcell. The device may include vertical bitlines coupled to the bitcell. The vertical bitlines may include multiple second read bitlines disposed in a vertical direction with respect to the bitcell.

公开(公告)号：US10521532B1

公开(公告)日：2019-12-31

申请号：US16125158

申请日：2018-09-07

Applicant: Arm Limited

Inventor： Pratik Ghanshambhai Satasia ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Hongwei Zhu ,  Mouli Rajaram Chollangi

IPC: G06F17/50 ,  G06F17/40

Abstract: Various implementations described herein refer to a method. The method may include selecting a target memory instance to characterize for timing file generation, determining a number of segments for the target memory instance based on user defined accuracy, and partitioning the target memory instance into the number of segments based on a physical architecture of the target memory instance. The method may also include generating test-bench data based on the number of segments and simulating the test-bench data, obtaining simulation data for the target memory instance associated with each segment in the number of segments, and generating a timing file by reporting timing data for each segment in the number of segments.

公开(公告)号：US10083269B2

公开(公告)日：2018-09-25

申请号：US14528314

申请日：2014-10-30

Applicant: ARM Limited

Inventor： Paul De Dood ,  Marlin Wayne Frederick ,  Jerry Chaoyuan Wang ,  Brian Douglas Ngai Lee ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Yanbin Jiang ,  Emmanuel Jean Marie Olivier Pacaud ,  Matthieu Domonique Henri Pauly ,  Sylvia Xiuhui Li ,  Thanusree Achuthan ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimized during generation of the layout of the cell.

公开(公告)号：US20250140310A1

公开(公告)日：2025-05-01

申请号：US18495834

申请日：2023-10-27

Applicant: Arm Limited

Inventor： Vivek Asthana ,  Andy Wangkun Chen ,  Ettore Amirante ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC: G11C11/412

Abstract: Various implementations described herein are directed to a device having an array of bitcells with a first bitcell disposed adjacent to a second bitcell. The device may have a first wordline coupled to first transistors in the first bitcell, and the device may have a second wordline coupled to second transistors in the second bitcell. Also, the device may have a buried ground line coupled to the first transistors and the second transistors.

公开(公告)号：US20250015133A1

公开(公告)日：2025-01-09

申请号：US18219292

申请日：2023-07-07

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Andy Wangkun Chen ,  Dileep Choorakuzhi Ramakrishnan ,  Subramanya Ravindra Shindagikar ,  Ala Srinivasa Rao

IPC: H01L29/06 ,  G06F30/392 ,  H01L27/092 ,  H01L29/78

Abstract: Various implementations described herein are directed to a device having a skew cell architecture with multiple diffusion regions including P-type diffusion regions disposed between N-type diffusion regions. The device may have power rails including a voltage supply rail disposed between ground rails. The device may have poly-gate rails disposed between the ground rails. The poly-gate rails may be cut to provide an open space between at least one N-type diffusion region and at least one P-type diffusion region.

公开(公告)号：US20240012748A1

公开(公告)日：2024-01-11

申请号：US17861084

申请日：2022-07-08

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F2212/1008

Abstract: According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.