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公开(公告)号:US10938498B2
公开(公告)日:2021-03-02
申请号:US16626463
申请日:2018-06-21
Applicant: INTEL IP CORPORATION
Inventor: Alexander Maltsev , Carlos Cordeiro , Artyom Lomayev , Michael Genossar , Claudio Da Silva
Abstract: An apparatus of a transmitter may include, for example, a Golay builder to build modulated Golay sequences for at least a non-EDMG Short Training Field (L-STF), and a non-EDMG Channel Estimation Field (L-CEF) of a PPDU; a scrambler to generate scrambled bits by scrambling bits of a non-EDMG header (L-header) and a data field of the PPDU; an encoder to encode the scrambled bits into encoded bits according to a low-density parity-check (LDPC) code; a constellation mapper to map the encoded bits into a stream of constellation points according to a constellation scheme; a spreader to spread the stream of constellation points according to a Golay sequence; and a transmit chain mapper to map a bit stream output from the Golay builder and the spreader to a plurality of transmit chains by applying a spatial expansion with relative cyclic shift over the plurality of transmit chains.
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82.
公开(公告)号:US10911118B2
公开(公告)日:2021-02-02
申请号:US16910243
申请日:2020-06-24
Applicant: INTEL IP CORPORATION
Inventor: Artyom Lomayev , Alexander Maltsev , Michael Genossar , Claudio Da Silva , Carlos Cordeiro
IPC: H04B7/06 , H04W80/02 , H04B7/0456
Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating a Physical Layer Protocol Data Unit (PPDU). For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) station (STA) may be configured to generate a Physical Layer (PHY) PPDU; generate one or more PPDU waveforms corresponding to one or more respective transmit chains for digital beamforming transmission of the PPDU; and transmit the PPDU via the one or more transmit chains over a channel bandwidth of at least 2.16 Gigahertz (GHz) in a frequency band above 45 GHz.
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83.
公开(公告)号:US20210006308A1
公开(公告)日:2021-01-07
申请号:US17028309
申请日:2020-09-22
Applicant: INTEL IP CORPORATION
Inventor: Artyom Lomayev , Claudio Da Silva , Michael Genossar , Alexander Maltsev , Carlos Cordeiro
IPC: H04B7/0456 , H04B7/06
Abstract: For example, an EDMG STA may generate an LDPC coded bit stream for a user based on data bits for the user in an EDMG PPDU, the LDPC coded bit stream for the user including a concatenation of a plurality of LDPC codewords, a count of the plurality of LDPC codewords is based at least on a codeword length for the user and on a code rate for the user; generate encoded and padded bits for the user by concatenating the LDPC coded bit stream with a plurality of coded pad zero bits, a count of the coded pad zero bits is based at least on a count of one or more spatial streams for the user and on the count of the plurality of LDPC codewords for the user; and distribute the encoded and padded bits for the user to the one or more spatial streams for the user.
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公开(公告)号:US10749974B2
公开(公告)日:2020-08-18
申请号:US15604108
申请日:2017-05-24
Applicant: Intel IP Corporation
Inventor: Emily H. Qi , Carlos Cordeiro , Ganesh Venkatesan , Bahareh Sadeghi
Abstract: Certain embodiments herein are directed to enabling service interoperability functionality for wireless fidelity (WiFi) Direct devices connected to a network via a wireless access point. A WiFi Direct device may identify various other WiFi Direct devices on a WiFi network for performing a requested service, such as printing content or displaying content to a screen. In so doing, the device may share information associated with an access point to which the device is connected with the other devices, which may also share information associated with an access point to which they are connected. In this way, WiFi Direct devices may discover their connectivity with respect to other devices to utilize a broader array of connection options for implementing a desired service, and hence, may leverage application programming interface (API) modules directed at providing service interoperability functionality between software applications and services requested by the software applications.
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85.
公开(公告)号:US10721761B2
公开(公告)日:2020-07-21
申请号:US16239202
申请日:2019-01-03
Applicant: Intel IP Corporation
Inventor: Laurent Cariou , Carlos Cordeiro , Chittabrata Ghosh , Assaf Kasher , Solomon B. Trainin
Abstract: Computer readable media, methods, and apparatuses for centralized channel access for primary and secondary channels are disclosed. An apparatus is disclosed comprising memory and processing circuitry. The processing circuitry is configured to encode a schedule of one or more resource allocations, wherein each resource allocation comprises a type of allocation, a bandwidth, an indication of a channel, a source association identification (AID), a destination AID, an allocation start, and a duration. The type of allocation may be a service period (SP) or a contention-based access period (CBAP). The channel may be an indication of a basic service set (BSS) or a personal BSS (PBSS) primary channel, BSS or PBSS secondary channel, or BSS or PBSS tertiary channel. The processing circuitry may be configured to transmit the schedule to one or more stations identified by the source AID and the destination AID of the one or more resource allocations.
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公开(公告)号:US20200228140A1
公开(公告)日:2020-07-16
申请号:US16624463
申请日:2018-06-18
Applicant: INTEL IP CORPORATION
Inventor: Artyom Lomayev , Alexander Maltsev , Michael Genossar , Claudio Da Silva , Carlos Cordeiro
Abstract: For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station (STA) may be configured to scramble, according to a first scrambling sequence, a plurality of EDMG Header B bits of an EDMG Header B field of an EDMG Multi-User (MU) Physical Layer (PHY) Protocol Data Unit (PPDU) into a plurality of scrambled header bits; generate a Low-Density Parity-Check (LDPC) codeword based on the plurality of scrambled header bits; determine a data block based on the LDPC codeword; generate one or more scrambled data blocks based on the data block by scrambling the data block according to a second scrambling sequence; and transmit a wireless transmission of the EDMG Header B based on the one or more scrambled data blocks.
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公开(公告)号:US20200067646A1
公开(公告)日:2020-02-27
申请号:US16488006
申请日:2018-03-22
Applicant: INTEL IP CORPORATION
Inventor: Artyom Lomayev , Alexander Maltsev , Michael Genossar , Claudio Da Silva , Carlos Cordeiro
Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating an Enhanced Directional Multi-Gigabit (DMG) (EDMG) Physical Layer Protocol Data Unit (PPDU). For example, an EDMG wireless communication station (STA) may be configured to communicate an EDMG PPDU including a Channel Estimation Field (CEF) and/or a pilot sequence, which may be configured for an OFDM mode.
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公开(公告)号:US10568027B2
公开(公告)日:2020-02-18
申请号:US15712101
申请日:2017-09-21
Applicant: INTEL IP CORPORATION
Inventor: Ou Yang , Carlos Cordeiro , Laurent Cariou , Chittabrata Ghosh , Solomon Trainin
IPC: H04B1/38 , H04W52/02 , H04B7/0452
Abstract: Techniques for power saving by remote wireless mobile devices are provided, in particular by stations (STAs) during downlink (DL) multiple-user multiple-input and multiple-output (MU-MIMO) transmissions in an Institute of Electrical and Electronics Engineers (IEEE) 802.11ay network when reverse direction (RD) transmissions are either enabled and not enabled. Various embodiments enable each STA in a group of STAs to determine an order in which the STAs are requested to send a block acknowledgement (BACK) and which STAs will be granted an RD transmission. Further, a duration of each RD transmission is provided to each STA. Based on the provided information, each STA can determine times to enter a power saving mode. Other embodiments are described and claimed.
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公开(公告)号:US20200037384A1
公开(公告)日:2020-01-30
申请号:US16538754
申请日:2019-08-12
Applicant: Intel IP Corporation
Inventor: Ou Yang , Solomon B. Trainin , Carlos Cordeiro , Cheng Chen
Abstract: A wireless communication device, system and method. The device includes a memory, a processing circuitry coupled to the memory and including logic, the processing circuitry to cause communication in an Enhanced Directional Multi-Gigabit (EDMG) network. The processing circuitry may be configured to: activate at least one Radio Frequency (RF) chain of a plurality of RF chains to allow detection of a preamble of a wireless communication and to allow a setting of a Network Allocation Vector (NAV); detect the preamble using the at least one RF chain; set the NAV using the at least one RF chain; maintain a backoff timer for the at least one RF chain; and, in response to a determination that the backoff timer has reached zero, cause a Multiple Input Multiple Output (MIMO) wireless communication in the EDMG network.
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90.
公开(公告)号:US20200021398A1
公开(公告)日:2020-01-16
申请号:US16583342
申请日:2019-09-26
Applicant: INTEL IP CORPORATION
Inventor: Artyom Lomayev , Alexander Maltsev , Michael Genossar , Claudio Da Silva , Carlos Cordeiro
Abstract: For example, an EDMG STA may be configured to generate a plurality of spatial streams of an EDMG PPDU; map the plurality of spatial streams to a respective plurality of pairs of space-time streams according to an STBC scheme by mapping a first data sequence of a spatial stream to a first symbol in an odd numbered space-time stream, mapping a second data sequence of the spatial stream to a second symbol in the odd numbered space-time stream, mapping a sign inverted complex conjugate of the second data sequence to a first symbol in an even numbered space-time stream, and mapping a complex conjugate of the first data sequence to a second symbol in the even numbered space-time stream; and transmit a transmission comprising the plurality of pairs of space-time streams over a channel bandwidth in a frequency band above 45 Gigahertz (GHz).
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