公开(公告)号：US07358823B2

公开(公告)日：2008-04-15

申请号：US11353516

申请日：2006-02-14

申请人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Jack A. Mandelman ,  William R. Tonti ,  Sebastian T. Ventrone

发明人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Jack A. Mandelman ,  William R. Tonti ,  Sebastian T. Ventrone

IPC分类号： H03B5/12

CPC分类号： H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03L7/095 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了一种调整半导体器件的电容的方法。 第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在 将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。 提供了许多其他方面。

公开(公告)号：US20080062748A1

公开(公告)日：2008-03-13

申请号：US11530981

申请日：2006-09-12

申请人： Pascal A. Nsame ,  Anthony J. Perri ,  Lansing U. Pickup ,  Sebastian T. Ventrone ,  Matthew R. Walland

发明人： Pascal A. Nsame ,  Anthony J. Perri ,  Lansing U. Pickup ,  Sebastian T. Ventrone ,  Matthew R. Walland

IPC分类号： G11C11/00

CPC分类号： G11C5/141 ,  G11C5/143 ,  G11C14/00

摘要： The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

摘要翻译： 本发明包括一种动态电压状态保存锁存电路，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号，数据信号 分配给所述充电装置的输入，从所述充电装置分配的数据信号以及分配给所述充电装置的时钟信号，其中所述集成恢复机构保持所述充电装置的状态而与所述充电装置无关。

公开(公告)号：US07257788B2

公开(公告)日：2007-08-14

申请号：US10904397

申请日：2004-11-08

申请人： Allen P. Haar ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Ivan L. Wemple

发明人： Allen P. Haar ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Ivan L. Wemple

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045

摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

摘要翻译： 公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。 最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。 根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。 在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

公开(公告)号：US07111151B2

公开(公告)日：2006-09-19

申请号：US09805200

申请日：2001-03-14

申请人： William P. Moore ,  Sebastian T. Ventrone

发明人： William P. Moore ,  Sebastian T. Ventrone

IPC分类号： G06F9/22

CPC分类号： G06F1/3243 ,  G06F1/3203 ,  G06F9/223 ,  G06F9/30145 ,  Y02D10/152

摘要： A microprocessor, method and signal-bearing medium for storing a program for executing the method, includes a microcode unit for outputting control signals, for each of a plurality of instructions, required by the microprocessor for executing the instructions. The microcode unit includes an instruction address input for receiving an instruction address, a control variable input for receiving a control variable corresponding to a current state of the microprocessor, a control signal input for receiving all of the control signals output by the microcode unit for an immediately preceding instruction, and a plurality of embedded logic circuits each dedicated for evaluating one unique type of instruction received by the microcode unit.

摘要翻译： 用于存储用于执行该方法的程序的微处理器，方法和信号承载介质包括微代码单元，用于为微处理器执行指令所需的多个指令的每一个输出控制信号。 微码单元包括用于接收指令地址的指令地址输入，用于接收与微处理器的当前状态相对应的控制变量的控制变量输入端，用于接收由微代码单元输出的所有控制信号的控制信号输入 以及多个嵌入式逻辑电路，每个专用于评估由微代码单元接收的一种唯一类型的指令。

公开(公告)号：US07085913B2

公开(公告)日：2006-08-01

申请号：US09683778

申请日：2002-02-13

申请人： W. Riyon Harding ,  Sebastian T. Ventrone

发明人： W. Riyon Harding ,  Sebastian T. Ventrone

IPC分类号： G06F15/17 ,  G06F17/50

CPC分类号： G06F15/7832

摘要： A method and structure for an integrated circuit is disclosed. The invention includes a plurality of logic cores, a plurality of local hubs connected to said logic cores, and a plurality of global hubs connected to said local hubs. The local hubs and the global hubs transfer data between the logic cores.

公开(公告)号：US06985004B2

公开(公告)日：2006-01-10

申请号：US09781369

申请日：2001-02-12

申请人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： H03K17/16

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

公开(公告)号：US06711719B2

公开(公告)日：2004-03-23

申请号：US09928573

申请日：2001-08-13

申请人： John Maxwell Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas Michael Lepsic ,  Patrick Edward Perry ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John Maxwell Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas Michael Lepsic ,  Patrick Edward Perry ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.

摘要翻译： 在集成电路（IC）设计中，功率消耗的分量可以表示为功率=½FCV <2>，其中C是由源单元驱动的负载电容，F是源单元的开关频率，V 是总输出电压摆幅。 然而，不是由源单元产生的每个信号值都不需要传播到芯片的每个时钟周期连接到源的所有宿单元。 因此，将隔离单元插入到将源单元连接到至少一个宿单元的网络（有线）中，以便当由所述源单元输出的信号从所述源单元输出时，将所述至少一个宿单元和所述网的一部分与所述源单元分离 源不需要传播。 由于去耦合，与至少一个接收器和净部分相关联的负载电容对于这种信号不被源单元体验。 因此，整体IC功耗降低。

公开(公告)号：US06412096B1

公开(公告)日：2002-06-25

申请号：US09303154

申请日：1999-04-30

申请人： Sebastian T. Ventrone

发明人： Sebastian T. Ventrone

IPC分类号： G06F1750

CPC分类号： G06F17/5022 ,  G06F17/505

摘要： An apparatus and method for performing a Hedge Technique Analysis are used to enhance the performance of the functional logic design of a large scale integrated circuit while simplifying the underlying logic. The methodology first runs performance tests on the logic circuitry to assess the timing and characterize the logic paths; next, functional paths are identified and listed; common logic path leaves, twigs, and branches are then identified and ranked by the number of critical paths associated with each; all high ranking common logic path leaves, twigs, and branches are then collapsed; and, timing paths are re-run to characterize the final performance rating of the functional design.

摘要翻译： 用于执行对冲技术分析的装置和方法用于增强大规模集成电路的功能逻辑设计的性能，同时简化基础逻辑。 该方法首先对逻辑电路执行性能测试，以评估逻辑路径的时序和特征; 接下来，确定并列出功能路径; 然后通过与每个相关联的关键路径的数量来识别和分级通用逻辑路径叶，树枝和分支; 然后，所有高排名的常见逻辑路径叶，树枝和树枝都崩溃了; 并且重新运行定时路径以表征功能设计的最终性能等级。

公开(公告)号：US06304122B1

公开(公告)日：2001-10-16

申请号：US09641425

申请日：2000-08-17

申请人： Roger P. Gregor ,  Steven F. Oakland ,  Toshiharu Saitoh ,  Sebastian T. Ventrone

发明人： Roger P. Gregor ,  Steven F. Oakland ,  Toshiharu Saitoh ,  Sebastian T. Ventrone

IPC分类号： H03K3289

CPC分类号： H03K3/0375 ,  H03K3/0372

摘要： This invention reduces power in flip flop apparatuses by providing flip flop apparatuses that have fewer clock trees than prior art flip flops yet still support some or all of the Level Sensitive Scan Design (LSSD) functionality. In preferred embodiments of the present invention, one clock tree is used instead of two to provide lower power, and less switching devices in clocks splitters are used, which also provides lower power. Additionally, a flushable single clock splitter is provided that allows one clock tree to be used up to the flushable single clock splitter and provides two clocks on the output of the flushable single clock splitter. This saves some power yet still allows for dual clock flip flop designs.

摘要翻译： 本发明通过提供具有比现有技术的触发器更少的时钟树的触发器装置来降低触发器装置的功率，但仍然支持一些或全部级别敏感扫描设计（LSSD）功能。 在本发明的优选实施例中，使用一个时钟树来代替两个时钟树来提供较低的功率，并且使用时钟分配器中的较少的开关器件，其也提供较低的功率。 另外，提供了一个可冲洗的单时钟分离器，其允许一个时钟树被使用到可冲洗的单时钟分离器，并且在可冲洗单时钟分离器的输出端上提供两个时钟。 这节省了一些功耗，但仍然允许双时钟触发器设计。

公开(公告)号：US06253299B1

公开(公告)日：2001-06-26

申请号：US09224793

申请日：1999-01-04

申请人： Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G06F1200

CPC分类号： G06F9/30112 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30138 ,  G06F12/0875

摘要： A structure and method for processing data comprises a processing unit having a base cache, base registers having a base width and being operatively connected to the processing unit, and virtual cache registers having a virtual width and being located in the base cache and operatively connected to the processing unit, wherein a base processing precision of the processing system is determined by the base width of the base registers and a selectable enhanced processing precision is determined by the virtual width of the virtual cache registers, wherein the base registers store base instructions and data and the virtual cache registers store enhanced data, the virtual width being greater than the base width, and wherein the base cache includes tags identifying a portion of the base cache as the virtual registers, the virtual cache registers being accessible by the processing unit only for execution of enhanced instructions for providing the enhanced processing precision.

摘要翻译： 用于处理数据的结构和方法包括具有基本高速缓存，具有基本宽度并且可操作地连接到处理单元的基本寄存器的处理单元和具有虚拟宽度并位于基本高速缓存中并可操作地连接到 所述处理单元，其中所述处理系统的基本处理精度由所述基本寄存器的基本宽度确定，并且可选择的增强处理精度由所述虚拟高速缓存寄存器的虚拟宽度确定，其中所述基本寄存器存储基本指令和数据 并且所述虚拟高速缓存寄存器存储增强数据，所述虚拟宽度大于所述基本宽度，并且其中所述基本高速缓存包括标识所述基本高速缓存的一部分作为所述虚拟寄存器的标签，所述虚拟高速缓存寄存器仅由所述处理单元访问 执行增强的指令以提供增强的处理精度。