Device for sterilizing packaging using hydrogen peroxide
    83.
    发明授权
    Device for sterilizing packaging using hydrogen peroxide 失效
    使用过氧化氢灭菌包装的装置

    公开(公告)号:US06786249B2

    公开(公告)日:2004-09-07

    申请号:US10362207

    申请日:2003-06-30

    CPC classification number: A61L2/208 A61L2/22 A61L2202/23 B65B55/10

    Abstract: Described is an apparatus for simultaneously sterilizing a large number of packs (1) by means of a gas mixture containing hydrogen peroxide and a carrier gas. The apparatus comprises: supply lines (4) for the carrier gas and for hydrogen peroxide (5), a device (21) for evaporating hydrogen peroxide by heat and mixing it into the carrier gas, supply lines (4, 5) and a substantially horizontally extending distributor line (6, 22) and nozzles (3) which are arranged above the respective pack (1) and are connected to the distributor line (6, 22). In order simultaneously to provide, with a simplification in the apparatus, measures by means of which the concentration of the hydrogen peroxide at all nozzles is maintained equal over the plurality of packs at a given time, the invention provides that the distributor line (6, 22) from the upstream location (23) of the in-feed of the conditioned gas mixture to the location (9) of entry upstream of the respective nozzle (3) is in the form of a tubular body including a longitudinal passage, with at least one substantially tubular heating cartridge (18) extending over the length of the tubular body and distributed measurement points (12) and that the heating cartridge (18) is divided into at least two portions and can be heated controlledly by a supply of electrical energy in such a way that the temperature at the outer ends of the tubular body (6) differs from the temperature at the center.

    Abstract translation: 描述了一种通过含有过氧化氢和载气的气体混合物同时对大量包装(1)进行灭菌的装置。 该装置包括:用于载气的供应管线(4)和用于过氧化氢(5)的装置,用于通过加热蒸发过氧化氢并将其混合到载气中的装置(21),供应管线(4,5)和基本上 水平延伸的分配器线(6,22)和喷嘴(3),其布置在相应的包装(1)上方并连接到分配器线(6,22)。 为了同时提供在设备中的简化,在给定时间,所有喷嘴上的过氧化氢浓度在多个包装上保持相等的措施,本发明提供了分配器管线(6, 从调节气体混合物的进料中的上游位置(23)到相应喷嘴(3)上游的入口位置(9)处于包括纵向通道的管状体的形式,其中在 至少一个基本上管状的加热筒(18),其延伸超过管状体的长度和分布的测量点(12),并且加热筒(18)被分成至少两个部分,并且可以通过电能供应 使得管状体(6)的外端的温度与中心处的温度不同。

    Method of transmitting clock signals, method of synchronizing clock generators or network elements, as well as a network element and a clock generator
    84.
    发明授权
    Method of transmitting clock signals, method of synchronizing clock generators or network elements, as well as a network element and a clock generator 失效
    传输时钟信号的方法,同步时钟发生器或网络元件的方法,以及网络元件和时钟发生器

    公开(公告)号:US06714610B1

    公开(公告)日:2004-03-30

    申请号:US09404319

    申请日:1999-09-24

    Applicant: Michael Wolf

    Inventor: Michael Wolf

    CPC classification number: H04J3/0647 H04J9/00 H04J2203/0089 H04L1/206

    Abstract: A method of transmitting clock signals (CS) in a synchronous digital communications network and a method of synchronizing clock generators (SSU) or network elements (SEC) wherein signaling of the clock quality is effected by phase-modulating the clock signal (CS). The clock signal (CS) is transmitted and received through simple clock interfaces (T4, CLO; T3, CLI) and contains a phase modulation characteristic of the clock quality. The phase modulation is detected and quality information is derived therefrom. Based on the quality information, the clock generator (SSU) or the network element (SEC) are synchronized to the clock signal. Also disclosed are a clock generator (SSU) and a network element (SEC; NE) for carrying out the two methods.

    Abstract translation: 一种在同步数字通信网络中发送时钟信号(CS)的方法和同步时钟发生器(SSU)或网络元件(SEC)的方法,其中通过对时钟信号(CS)进行相位调制来实现时钟质量的信令。 时钟信号(CS)通过简单的时钟接口(T4,CLO; T3,CLI)发送和接收,并包含时钟质量的相位调制特性。 检测相位调制,并从中导出质量信息。 基于质量信息,时钟发生器(SSU)或网元(SEC)与时钟信号同步。 还公开了一种用于执行两种方法的时钟发生器(SSU)和网络元件(SEC; NE)。

    Method for unrolling two-deep loops with convex bounds and imperfectly nested code, and for unrolling arbitrarily deep nests with constant bounds and imperfectly nested code
    85.
    发明授权
    Method for unrolling two-deep loops with convex bounds and imperfectly nested code, and for unrolling arbitrarily deep nests with constant bounds and imperfectly nested code 失效
    用于展开具有凸边界和不完全嵌套代码的双深环的方法,以及用于展开具有常量边界和不完全嵌套代码的任意深度的嵌套

    公开(公告)号:US06567976B1

    公开(公告)日:2003-05-20

    申请号:US08822927

    申请日:1997-03-20

    Applicant: Michael Wolf

    Inventor: Michael Wolf

    CPC classification number: G06F8/443

    Abstract: A compiler for compiling source code whereby the compiled source code is optimized by performing outer loop unrolling (a generalization of “unroll and jam” on selected loop nests. The present invention allows any arbitrarily deep loop nests with non-varying loop bounds to be properly unrolled even in the presence of imperfectly nested code. This is accomplished for two-deep loop nests by transforming the code into multiple adjacent loop nests. In the transformed code, the imperfect code is isolated so that one of the adjacent loops nests has none, and thus can be unrolled and jammed. For three-deep or greater loop nests, the process is repeated recursively from the outer-most loop. The present invention also allows outer loop unrolling for two-deep loop nests with convex bounds, even with the presence of imperfectly nested code. This is accomplished by identifying strips of code which do not contain imperfectly nested code. An unroll and jam operation is executed for the identified strips. Code falling outside of the identified strips as well as wind-down code, are executed according to their original, untransformed order.

    Abstract translation: 一种用于编译源代码的编译器,通过执行外部循环展开(在选定的循环嵌套上进行“展开和阻塞”)的泛化,编译的源代码被优化。本发明允许具有非变化循环边界的任意任意的深循环嵌套适当地 即使在存在不完全嵌套的代码的情况下也可以展开,这通过将代码转换成多个相邻的循环嵌套来实现双深度嵌套,在转换的代码中,不完美的代码被隔离,使得相邻的循环嵌套之一没有, 因此可以展开和堵塞,对于三深或更大的环形巢,该过程从最外环循环重复,本发明还允许外循环展开具有凸边界的双深环巢,即使 存在不完全嵌套的代码,这是通过识别不包含不完全嵌套代码的代码段来实现的,为所识别的str执行展开和果酱操作 ips。 根据其原始,未转换的顺序执行掉在识别的条带外的代码以及下降代码。

    Isoxazole derivatives to be used as phosphodiesterase VII inhibitors
    86.
    发明授权
    Isoxazole derivatives to be used as phosphodiesterase VII inhibitors 失效
    异恶唑衍生物用作磷酸二酯酶VII抑制剂

    公开(公告)号:US06531498B1

    公开(公告)日:2003-03-11

    申请号:US10129270

    申请日:2002-05-03

    CPC classification number: A61K31/42

    Abstract: The invention relates to compounds of formula I and to their physiologically acceptable salts and solvates which act as phosphodiesterse VII inhibitors and are thus useful for the treatment of allergic disorders, asthma, chronic bronchitis, atopic dermatitis, psoriasis and other skin disorders, inflammatory disorders, autoimmune diseases, rheumatoid arthritis, multiple sclerosis, Crohn's disease, diabetes mellitus or ulcerative colitis, osteoporosis, transplant rejection reactions, cachexia, tumor growth, tumor metastases, sepsis, memory disturbances, atherosclerosis and AIDS.

    Abstract translation: 本发明涉及式I化合物及其作为磷酸二酯VII抑制剂的生理上可接受的盐和溶剂合物,因此可用于治疗过敏性疾病,哮喘,慢性支气管炎,特应性皮炎,牛皮癣和其他皮肤病,炎症性疾病, 自身免疫疾病,类风湿性关节炎,多发性硬化,克罗恩病,糖尿病或溃疡性结肠炎,骨质疏松症,移植排斥反应,恶病质,肿瘤生长,肿瘤转移,败血症,记忆障碍,动脉粥样硬化和艾滋病。

    Synchronization device for a synchronous digital message transmission system and process for producing a synchronous output signal
    87.
    发明授权
    Synchronization device for a synchronous digital message transmission system and process for producing a synchronous output signal 失效
    用于同步数字消息传输系统的同步装置和用于产生同步输出信号的过程

    公开(公告)号:US06526069B1

    公开(公告)日:2003-02-25

    申请号:US09244628

    申请日:1999-02-04

    Abstract: A synchronization device for a synchronous digital message transmission system producing a synchronous output signal including successive transport modules synchronized to a frame clock from a digital input signal. The synchronization device includes a receiver unit for receiving the input signal, a packet assembly device for packaging the input signal into subassemblies of the transport modules, a buffer memory, a writer for writing data bits of the input signal out of the subassemblies into the buffer memory with a write clock, a reader, for reading data bits out of the buffer memory with a read clock in order to form the output signal, and a sending unit (SO) for sending synchronous output signals. The effective bit rate of the subassemblies compared to the standardized value is either lowered or raised by selecting the write clock lower than the read clock.

    Abstract translation: 一种用于同步数字消息传输系统的同步装置,其产生包括从数字输入信号与帧时钟同步的连续传输模块的同步输出信号。 同步装置包括用于接收输入信号的接收器单元,用于将输入信号封装到传输模块的子组件中的分组组装装置,缓冲存储器,写入器,用于将输入信号的数据位从子组件写入缓冲器 具有写入时钟的存储器,读取器,用于以读取时钟从缓冲存储器读出数据位以形成输出信号;以及发送单元(SO),用于发送同步输出信号。 通过选择低于读时钟的写时钟,子组件与标准化值相比的有效位速率降低或升高。

    Process and devices for establishing point-to-multipoint connections and multipoint-to-point connections
    88.
    发明授权
    Process and devices for establishing point-to-multipoint connections and multipoint-to-point connections 失效
    用于建立点对多点连接和多点到点连接的过程和设备

    公开(公告)号:US06418142B1

    公开(公告)日:2002-07-09

    申请号:US09153704

    申请日:1998-09-15

    Applicant: Michael Wolf

    Inventor: Michael Wolf

    CPC classification number: H04Q11/0478 H04J2203/0019 H04J2203/006

    Abstract: The present invention relates to a process for establishing point-to-multipoint connections (A14, A33, A34) and multipoint-to-point connections (B14, B15, B35) in a coupling field comprised of a number of stages (I, II, III), each with a number of switching modules (11-15, 21-25, 31-35). To that end, when there are switching modules (21-25) in at least one stage (II), and if, depending on their type, these switching modules are capable of simultaneously splitting point-to-multipoint connections (A14, A33, A34) and of coupling together multipoint-to-point connections (B14, B15, B35), the proposition is made to connect point-to-multipoint connections (A14, A33, A34) in switching modules (25) in which more inputs than outputs are already loaded with connections and to connect multipoint-to-point connections (B14, B15, B35) by switching modules (24) in which more outputs than inputs are already loaded with connections.

    Abstract translation: 本发明涉及在由多个级(I,II)组成的耦合场中建立点对多点连接(A14,A33,A34)和多点到点连接(B14,B15,B35)的过程 ,III),每个具有多个开关模块(11-15,21-25,31-35)。 为此,当在至少一个阶段(II)中存在切换模块(21-25)时,如果根据其类型,这些交换模块能够同时分离点对多点连接(A14,A33, A34)并且将多点到点连接(B14,B15,B35)耦合在一起,该命题用于连接交换模块(25)中的点对多点连接(A14,A33,A34),其中更多的输入比 输出端已经加载了连接,并通过切换模块(24)连接多点到点连接(B14,B15,B35),其中输入比输入端更多的输出已经加载了连接。

    Synchronous digital communications system and control installation
    89.
    发明授权
    Synchronous digital communications system and control installation 有权
    同步数字通信系统和控制安装

    公开(公告)号:US06411633B1

    公开(公告)日:2002-06-25

    申请号:US09697535

    申请日:2000-10-26

    Applicant: Michael Wolf

    Inventor: Michael Wolf

    CPC classification number: H04J3/0647 H04J3/0688 H04J2203/0042 H04J2203/006

    Abstract: The network elements NE1, . . . , NE6 of a synchronous digital communications system must be synchronized with each other without the possibility of clock loops occurring. A network node NODE contains network elements NE1, . . . , NE6 and a central clock generator SASE. The network elements transmit clock signals 2M to the clock generator, which contain a clock of a message signal STM-N and a quality indicator (SSM) contained in the message signal which reflects the accuracy of the clock. The clock generator selects one of the clock signals 2M as the reference clock REF and informs the control installation STE which of the clock signals it has selected and the degree of accuracy of this clock signal. On the basis of this message STAT the control installation gives instructions ANW to the network elements with respect to the quality indicator which the network elements are to transmit to their outputs.

    Abstract translation: 网元NE1,。 。 。 ,同步数字通信系统的NE6必须彼此同步,而不会发生时钟环路。 网络节点NODE包含网元NE1,。 。 。 ,NE6和中央时钟发生器SASE。 网络元件将时钟信号2M发送到时钟发生器,时钟发生器包含消息信号STM-N的时钟和反映时钟精度的消息信号中包含的质量指示符(SSM)。 时钟发生器选择一个时钟信号2M作为参考时钟REF,并通知控制装置STE它选择了哪个时钟信号以及该时钟信号的精度。 在此消息STAT的基础上,控制设备向网络元件提供关于网络元件要向其输出传输的质量指示符的指令ANW。

    Synchronous digital communication system with a hierarchical
synchronization network
    90.
    发明授权
    Synchronous digital communication system with a hierarchical synchronization network 失效
    具有分层同步网络的同步数字通信系统

    公开(公告)号:US5886996A

    公开(公告)日:1999-03-23

    申请号:US573388

    申请日:1995-12-15

    Applicant: Michael Wolf

    Inventor: Michael Wolf

    CPC classification number: H04J3/0647 H04J3/0679 H04J2203/0089

    Abstract: In synchronous digital communication systems using a synchronization quality marker (SSM), timing loops can be created. To avoid such timing loops, a synchronous digital communication system is provided having network elements (NE11, . . . , NE33) in which two classes (top, bottom) are defined for interface units (S.sub.1, . . . , S.sub.x, . . . , S.sub.X+i).

    Abstract translation: 在使用同步质量标记(SSM)的同步数字通信系统中,可以创建定时循环。 为了避免这种定时环路,提供了具有网络元件(NE11,...,NE33)的同步数字通信系统,其中为接口单元(S1,...,Sx,...)定义了两个类(顶部,底部) 。,SX + i)。

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