公开(公告)号：US20200319882A1

公开(公告)日：2020-10-08

申请号：US16592500

申请日：2019-10-03

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Nadav Grosz

IPC: G06F9/30 ,  G06F9/48 ,  G06F3/06

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a large read operation can include receiving a pre-fetch command, a parameter list and a read command at a storage system. In certain examples, the pre-fetch command can provide an indication of the length of the parameter list, and the parameter list can provide location identifiers of the storage system from which the read command can sense the read data.

公开(公告)号：US20200210097A1

公开(公告)日：2020-07-02

申请号：US16235168

申请日：2018-12-28

Applicant: Micron Technology, Inc

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can be determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.

公开(公告)号：US20200210080A1

公开(公告)日：2020-07-02

申请号：US16237134

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.