公开(公告)号：US08130044B2

公开(公告)日：2012-03-06

申请号：US12142746

申请日：2008-06-19

申请人： William W. Bereza ,  Rakesh H. Patel

发明人： William W. Bereza ,  Rakesh H. Patel

IPC分类号： H03L7/00

CPC分类号： H03L7/099 ,  H03L7/18

摘要： Configurable phase-locked loop circuitry is provided. The phase-locked loop circuitry may include a buffer having a buffer output and a multiplexer having inputs and an output. The phase-locked loop circuitry may include multiple voltage-controlled oscillators. The phase-locked loop circuitry may be configured to switch a desired one of the voltage-controlled oscillators into use. Each voltage-controlled oscillator may be controlled by control signals applied to a control input for that voltage-controlled oscillator. The control input of each voltage-controlled oscillator may be connected to the buffer output. The output of each voltage-controlled oscillator may be connected to a respective one of the multiplexer inputs. Power-down transistors may be used to disable unused voltage-controlled oscillators to conserve power. The power-down transistors and the multiplexer may be controlled by signals from programmable elements. One or more of the voltage-controlled oscillators may be implemented using a separate integrated circuit connected using through-silicon vias.

摘要翻译： 提供可配置的锁相环电路。 锁相环电路可以包括具有缓冲器输出的缓冲器和具有输入和输出的多路复用器。 锁相环电路可以包括多个压控振荡器。 锁相环电路可以被配置为将期望的一个压控振荡器切换成使用。 每个压控振荡器可以由施加到该压控振荡器的控制输入的控制信号来控制。 每个压控振荡器的控制输入可以连接到缓冲器输出端。 每个压控振荡器的输出可以连接到多路复用器输入中的相应一个。 掉电晶体管可用于禁用未使用的电压控制振荡器以节省功率。 掉电晶体管和多路复用器可以由来自可编程元件的信号控制。 可以使用通过硅通孔连接的单独的集成电路来实现一个或多个压控振荡器。

公开(公告)号：US07698482B2

公开(公告)日：2010-04-13

申请号：US11177007

申请日：2005-07-08

申请人： Ramanand Venkata ,  Rakesh H. Patel ,  Chong H. Lee

发明人： Ramanand Venkata ,  Rakesh H. Patel ,  Chong H. Lee

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： H03K19/17744

摘要： A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.

摘要翻译： 用于可编程逻辑器件的串行接口通过提供支持第一范围的数据速率的第一数量的通道和支持第二数据速率范围的第二数量的通道来支持宽范围的数据速率。 数据速率的第一范围优选地低于数据速率的第二范围，并且优选地，第一数量的信道高于优选为1的信道的第二数量。为了与现有设备的向后兼容，每个信道中的第一数量的信道 界面最好是四。 每个通道优选地包括物理介质连接模块和物理编码子层模块。 第二数量的频道中的每一个较高频道优选地还包括时钟管理单元，而第一数量的频道中的较低速频道优选地共享一个或多个时钟管理单元。

公开(公告)号：US07693691B1

公开(公告)日：2010-04-06

申请号：US11524012

申请日：2006-09-19

申请人： Yuming Tao ,  William W. Bereza ,  Rakesh H. Patel ,  Tad Kwasniewski ,  Sergey Shumarayev ,  Shoujun Wang ,  Miao Li

发明人： Yuming Tao ,  William W. Bereza ,  Rakesh H. Patel ,  Tad Kwasniewski ,  Sergey Shumarayev ,  Shoujun Wang ,  Miao Li

IPC分类号： G06F17/50 ,  H04B1/04

CPC分类号： G06F17/5009

摘要： Systems and methods for accurately and quickly simulating link performance of a transceiver operating with any given transmission medium are provided. Accurate and quick link simulations may be provided using a link simulation platform. The link simulation platform may simulate link performance using transceiver behavioral models (e.g., transmitter and receiver behavioral models) that incorporate silicon level parameters, which parameters enable the behavioral models to substantially emulate the actual behavior of the transceiver portions of the link.

摘要翻译： 提供了用于准确和快速地模拟使用任何给定传输介质工作的收发器的链路性能的系统和方法。 可以使用链路仿真平台提供准确和快速的链路模拟。 链路仿真平台可以使用包含硅级参数的收发机行为模型（例如，发射机和接收机行为模型）来模拟链路性能，这些参数使得行为模型能够基本上模拟链路的收发器部分的实际行为。

公开(公告)号：US20090279597A1

公开(公告)日：2009-11-12

申请号：US12117515

申请日：2008-05-08

申请人： William W. Bereza ,  Albert Vareljian ,  Rakesh H. Patel

发明人： William W. Bereza ,  Albert Vareljian ,  Rakesh H. Patel

IPC分类号： H04L27/01

CPC分类号： H04L25/0272

摘要： Incoming data at a high-speed serial receiver is digitized and then digital signal processing (DSP) techniques may be used to perform digital equalization. Such digital techniques may be used to correct various data anomalies. In particular, in a multi-channel system, where crosstalk may be of concern, knowledge of the characteristics of the other channels, or even the data on those channels, may allow crosstalk to be subtracted out. Knowledge of data channel geometries, particularly in the context of backplane transmissions, may allow echoes and reflections caused by connectors to be subtracted out. As data rates increase, fractional rate processing can be employed. For example, the analog-to-digital conversion can be performed at half-rate and then two DSPs can be used in parallel to maintain throughput at the higher initial clock rate. At even higher rates, quadrature techniques can allow analog-to-digital conversion at quarter-rate, with four DSPs used in parallel.

摘要翻译： 数字化高速串行接收机的传入数据，然后可以使用数字信号处理（DSP）技术来执行数字均衡。 这样的数字技术可以用于校正各种数据异常。 特别地，在可能涉及串扰的多通道系统中，其他通道的特性或甚至这些通道上的数据的知识可能允许减去串扰。 对数据通道几何的了解，特别是在背板传输的上下文中，可能允许减去连接器引起的回波和反射。 随着数据速率的提高，可以采用分数速率处理。 例如，可以以半速率执行模数转换，然后可以并行使用两个DSP，以在较高的初始时钟速率下维持吞吐量。 在更高的速率下，正交技术可以允许以四分之一速率进行模数转换，并行使用四个DSP。

公开(公告)号：US06570404B1

公开(公告)日：2003-05-27

申请号：US08824535

申请日：1997-03-26

申请人： Kevin A. Norman ,  Rakesh H. Patel ,  Stephen P. Sample ,  Michael R. Butts

发明人： Kevin A. Norman ,  Rakesh H. Patel ,  Stephen P. Sample ,  Michael R. Butts

IPC分类号： H03K19177

CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

摘要： A programmable logic device architecture. This programmable logic architecture includes a first logic block (425) containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface (415), which interfaces with the first logic block (425), for performing JTAG functions, configuring the first logic block (425), initializing the first logic block (425), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block (425) may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network (511). The first logic block (425) includes a plurality of second logic blocks (505) which may be programmably coupled using a second programmable interconnect network (521). The second programmable interconnect network (521) may be programmably coupled to the first programmable interconnect network (511). Furthermore, the plurality of second logic blocks (505) include a plurality of third logic blocks (525) which may be programmably coupled using a third programmable interconnect network (535). A signal from a third logic block (525) may be programmably coupled to the other logic blocks, the diagnostic block interface (415), and other circuitry on the integrated circuit. The internal circuitry of these logic blocks may be monitored through a variety of programmable interconnect paths. This architecture is useful when debugging a design, especially for emulation and prototyping applications.

摘要翻译： 可编程逻辑器件架构。 该可编程逻辑架构包括包含用于执行逻辑功能的可编程逻辑元件的第一逻辑块（425）。 该结构还可以包括诊断块接口（415），其与第一逻辑块（425）接口，用于执行JTAG功能，配置第一逻辑块（425），初始化第一逻辑块（425），与接口关闭 芯片诊断和测试设备和设备，并执行其他类似功能。 第一逻辑块（425）可以使用第一可编程互连网络（511）可编程地耦合到集成电路上的其他组件。 第一逻辑块（425）包括可以使用第二可编程互连网络（521）可编程地耦合的多个第二逻辑块（505）。 第二可编程互连网络（521）可以可编程地耦合到第一可编程互连网络（511）。 此外，多个第二逻辑块（505）包括可以使用第三可编程互连网络（535）可编程地耦合的多个第三逻辑块（525）。 来自第三逻辑块（525）的信号可以可编程地耦合到其他逻辑块，诊断块接口（415）和集成电路上的其它电路。 这些逻辑块的内部电路可以通过各种可编程互连路径进行监控。 这种架构在调试设计时非常有用，特别是对于仿真和原型应用。

公开(公告)号：US06467017B1

公开(公告)日：2002-10-15

申请号：US09124649

申请日：1998-07-29

申请人： Tony K. Ngai ,  Rakesh H. Patel ,  Srinivas T. Reddy ,  Richard G. Cliff

发明人： Tony K. Ngai ,  Rakesh H. Patel ,  Srinivas T. Reddy ,  Richard G. Cliff

IPC分类号： G06F1200

CPC分类号： H03K19/1776 ,  G11C7/1075 ,  G11C2207/104 ,  H03K19/17736

摘要： A programmable logic device has embedded random access memory (“RAM”) that can function equally well in either single-port or dual-port operation. The RAM is dual-port RAM whose read address inputs and write address inputs are both connected to a conductor bus via two different sparsely populated programmable interconnection resources. The programmable interconnection resources are arranged so that each pair of corresponding read address and write address inputs can be connected to at least one conductor in common on the conductor bus, allowing the RAM to be configured to mimic a single-port RAM as read address signals and write address signals originating at remote components of the programmable logic device “think” they are being directed to the same address inputs.

摘要翻译： 可编程逻辑器件具有嵌入式随机存取存储器（“RAM”），其可在单端口或双端口操作中同等功能。 RAM是双端口RAM，其读地址输入和写地址输入都通过两个不同的稀疏布置的可编程互连资源连接到导体总线。 可编程互连资源被布置为使得每对相应的读取地址和写入地址输入可以在导体总线上共同连接到至少一个导体，从而允许RAM被配置为模拟单端口RAM作为读取地址信号 并且写入源自可编程逻辑器件的远程组件的地址信号“认为”它们被引导到相同的地址输入。

公开(公告)号：US06243304B1

公开(公告)日：2001-06-05

申请号：US09441143

申请日：1999-11-12

申请人： Rakesh H. Patel ,  Kevin A. Norman

发明人： Rakesh H. Patel ,  Kevin A. Norman

IPC分类号： G11C700

CPC分类号： G06F17/5027 ,  G01R31/318516 ,  G01R31/318536 ,  G11C7/1006 ,  G11C29/48 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776 ,  H03K19/17764

摘要： A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes such as logic element registers, memory cells, and I/O registers. A sample/load data path includes bidirectional data buses and shift register that facilitate the sampling of internal nodes for observing their logic states, and loading of internal nodes for controlling their logic states.

摘要翻译： 公开了一种可编程逻辑器件（PLD），它提供观察和控制埋入式内部节点的逻辑状态的能力。 PLD为内部节点提供影子存储单元，例如逻辑单元寄存器，存储单元和I / O寄存器。 样本/负载数据路径包括双向数据总线和移位寄存器，便于对内部节点进行采样以观察其逻辑状态，并加载内部节点以控制其逻辑状态。

公开(公告)号：US6014334A

公开(公告)日：2000-01-11

申请号：US12667

申请日：1998-01-23

申请人： Rakesh H. Patel ,  Kevin A. Norman

发明人： Rakesh H. Patel ,  Kevin A. Norman

IPC分类号： G01R31/3185 ,  G06F17/50 ,  G11C7/10 ,  H03K19/177 ,  G11C7/00

CPC分类号： G06F17/5027 ,  G01R31/318516 ,  G01R31/318536 ,  G11C29/48 ,  G11C7/1006 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776 ,  H03K19/17764

摘要： A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes such as logic element registers, memory cells, and I/O registers. A sample/load data path includes bidirectional data buses and shift register that facilitate the sampling of internal nodes for observing their logic states, and loading of internal nodes for controlling their logic states.

摘要翻译： 公开了一种可编程逻辑器件（PLD），它提供观察和控制埋入式内部节点的逻辑状态的能力。 PLD为内部节点提供影子存储单元，例如逻辑单元寄存器，存储单元和I / O寄存器。 样本/负载数据路径包括双向数据总线和移位寄存器，便于对内部节点进行采样以观察其逻辑状态，并加载内部节点以控制其逻辑状态。

公开(公告)号：US6011744A

公开(公告)日：2000-01-04

申请号：US895516

申请日：1997-07-16

申请人： Stephen P. Sample ,  Michael R. Butts ,  Kevin A. Norman ,  Rakesh H. Patel ,  Chao Chiang Chen

发明人： Stephen P. Sample ,  Michael R. Butts ,  Kevin A. Norman ,  Rakesh H. Patel ,  Chao Chiang Chen

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/16 ,  H03K19/177 ,  G11C8/00

CPC分类号： H03K19/17772 ,  G11C7/1006 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/16 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778 ,  H03K19/177

摘要： An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.

公开(公告)号：US6011730A

公开(公告)日：2000-01-04

申请号：US298890

申请日：1999-04-23

申请人： Stephen P. Sample ,  Michael R. Butts ,  Kevin A. Norman ,  Rakesh H. Patel ,  Chao Chiang Chen

发明人： Stephen P. Sample ,  Michael R. Butts ,  Kevin A. Norman ,  Rakesh H. Patel ,  Chao Chiang Chen

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/16 ,  H03K19/177 ,  G11C7/00

CPC分类号： H03K19/17772 ,  G11C7/1006 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/16 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778 ,  H03K19/177

摘要： An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.