-
公开(公告)号：US09588762B2
公开(公告)日：2017-03-07
申请号：US13421442
申请日：2012-03-15
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/30047 , G06F9/30185 , G06F9/45516
摘要： Processing of character data is facilitated. A Find Element Not Equal instruction is provided that compares data of multiple vectors for inequality and provides an indication of inequality, if inequality exists. An index associated with the unequal element is stored in a target vector register. Further, the same instruction, the Find Element Not Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare.
摘要翻译： 字符数据的处理方便。 一个查找元素提供不等式的指令，用于比较不等式的多个向量的数据，并提供不平等的指示，如果存在不等式。 与不等元素相关联的索引存储在目标向量寄存器中。 此外，相同的指令“Find Element Not Equal”（查找元素不相等）指令也会搜索所选向量的零元素，也称为零元素。 指令的结果取决于是否提供空搜索，还是只是比较。
-
公开(公告)号：US09459864B2
公开(公告)日：2016-10-04
申请号：US13421560
申请日：2012-03-15
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/3016 , G06F9/30185
摘要： Processing of character data is facilitated. A Vector String Range Compare instruction is provided that compares each element of a vector with a range of values based on a set of controls to determine if there is a match. An index associated with the matched element or a mask representing the matched element is stored in a target vector register. Further, the same instruction, the Vector String Range Compare instruction, also searches a selected vector for null elements, also referred to as zero elements.
摘要翻译： 字符数据的处理方便。 矢量字符串范围提供比较指令，它将矢量的每个元素与基于一组控件的值范围进行比较，以确定是否存在匹配。 与匹配元素相关联的索引或表示匹配元素的掩码存储在目标向量寄存器中。 此外，相同的指令矢量字符串范围比较指令也会搜索所选向量的零元素，也称为零元素。
-
83.发明申请公开(公告)号：US20130247009A1
公开(公告)日：2013-09-19
申请号：US13422563
申请日：2012-03-16
IPC分类号： G06F9/44
CPC分类号： G06F9/30145 , G06F9/3005 , G06F9/30058 , G06F11/3466 , G06F11/348 , G06F11/3644 , G06F2201/86 , G06F2201/88
摘要： Embodiments of the invention relate to implementing run-time instrumentation indirect sampling by instruction operation code. An aspect of the invention includes reading sample-point instruction operation codes from a sample-point instruction array, and comparing, by a processor, the sample-point instruction operation codes to an operation code of an instruction from an instruction stream executing on the processor. A sample point is recognized upon execution of the instruction with the operation code matching one of the sample-point instruction operation codes. The run-time instrumentation information is obtained from the sample point. The run-time instrumentation information is stored in a run-time instrumentation program buffer as a reporting group.
摘要翻译： 本发明的实施例涉及通过指令操作代码实现运行时间仪表间接采样。 本发明的一个方面包括从采样点指令阵列读取采样点指令操作码，并将处理器将采样点指令操作码与来自在处理器上执行的指令流的指令的操作码进行比较 。 在执行指令时，识别采样点，其中操作码与采样点指令操作码之一匹配。 从采样点获取运行时仪表信息。 运行时仪表信息作为报告组存储在运行时仪表程序缓冲区中。
-
公开(公告)号：US20130246751A1
公开(公告)日：2013-09-19
申请号：US13421442
申请日：2012-03-15
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/30047 , G06F9/30185 , G06F9/45516
摘要： Processing of character data is facilitated. A Find Element Not Equal instruction is provided that compares data of multiple vectors for inequality and provides an indication of inequality, if inequality exists. An index associated with the unequal element is stored in a target vector register. Further, the same instruction, the Find Element Not Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare.
-
公开(公告)号：US08161091B2
公开(公告)日：2012-04-17
申请号：US12358911
申请日：2009-01-23
申请人： Steven R. Carlough , Wen H. Li , Eric M. Schwarz
发明人： Steven R. Carlough , Wen H. Li , Eric M. Schwarz
IPC分类号： G06F7/485
CPC分类号： G06F7/4912 , G06F2207/4911
摘要： A method for performing a decimal floating point operation including receiving a first operand having a first coefficient and a first exponent into a first register. A second operand having a second coefficient and a second exponent are received into a second register. An operation, either addition or subtraction, associated with the first operand and the second operand is received. Three concurrent calculations are performed on the first operand and the second operand. The three concurrent calculations include: applying the operation to the first operand and the second operand based on a first assumption; applying the operation to the first operand and the second operand based on a second assumption; and applying the operation to the first operand and the second operand based on a third assumption. A final result is selected from the first result, the second result and the third result.
摘要翻译： 一种用于执行十进制浮点运算的方法，包括将具有第一系数和第一指数的第一操作数接收到第一寄存器中。 具有第二系数和第二指数的第二操作数被接收到第二寄存器中。 接收与第一操作数和第二操作数相关联的加法或减法操作。 在第一个操作数和第二个操作数上执行三个并发计算。 三个并发计算包括：基于第一假设将操作应用于第一操作数和第二操作数; 基于第二假设将操作应用于第一操作数和第二操作数; 以及基于第三假设将所述操作应用于所述第一操作数和所述第二操作数。 从第一个结果，第二个结果和第三个结果中选择最终结果。
-
86.发明授权System and method for converting from scaled binary coded decimal into decimal floating point 有权从缩放二进制编码十进制转换为十进制浮点的系统和方法公开(公告)号：US07698352B2
公开(公告)日：2010-04-13
申请号：US11227515
申请日：2005-09-15
IPC分类号： G06F15/00
摘要： A system and method for converting from scaled binary coded decimal (SBCD) into decimal floating point (DFP). The system includes a mechanism for receiving one or more of an exponent part of a SBCD number and a coefficient part of the SBCD number. The system also includes at least one of a mechanism for performing coefficient compression on the coefficient part of the SBCD number to create a coefficient part of a DFP number and a mechanism for performing exponent insertion including inserting the exponent part of the SBCD number into an exponent part of the DFP number.
摘要翻译： 从缩放二进制编码十进制（SBCD）转换为十进制浮点（DFP）的系统和方法。 该系统包括用于接收SBCD号的指数部分和SBCD号的系数部分中的一个或多个的机构。 该系统还包括用于对SBCD号码的系数部分执行系数压缩以创建DFP号码的系数部分的机制和用于执行指数插入的机制中的至少一个，包括将SBCD号码的指数部分插入指数 DFP编号的一部分。
-
公开(公告)号：US20090210659A1
公开(公告)日：2009-08-20
申请号：US12032105
申请日：2008-02-15
CPC分类号： G06F9/3861 , G06F9/3017 , G06F9/322 , G06F9/328 , G06F11/0721 , G06F11/0793
摘要： A processor includes a microarchitecture for working around a processing flaw, the microarchitecture including: at least one detector adapted for detecting a predetermined state associated with the processing flaw; and at least one mechanism to modify default processor processing behavior; and upon modification of processing behavior, the processing of an instruction involving the processing flaw can be completed by avoiding the processing flaw.
摘要翻译： 处理器包括用于处理加工缺陷的微架构，所述微体系结构包括：至少一个检测器，适于检测与所述处理缺陷相关联的预定状态; 以及至少一种修改默认处理器处理行为的机制; 并且在修改处理行为时，可以通过避免处理缺陷来完成涉及处理缺陷的指令的处理。
-
公开(公告)号：US20090132628A1
公开(公告)日：2009-05-21
申请号：US12358885
申请日：2009-01-23
IPC分类号： G06F7/52
CPC分类号： G06F7/4917 , G06F2207/5352
摘要： A method for performing decimal division including receiving a scaled divisor and a scaled dividend into input registers. A subset of multiples of the scaled divisor is stored in a plurality of multiples registers. Quotient digits are calculated in response to the scaled divisor and the scaled dividend. Each quotient digit is calculated in three clock cycles by a pipeline mechanism. The calculating includes selecting a new quotient digit, and calculating a new remainder. Input to the calculating a new remainder includes data from one or more of the multiples registers.
摘要翻译： 一种用于执行小数除法的方法，包括将输入寄存器中的缩放除数和缩放的除数接收。 缩放除数的倍数的子集存储在多个多个寄存器中。 商数是根据缩放除数和缩放除数计算的。 每个商数由流水线机构在三个时钟周期内计算。 计算包括选择新的商数，并计算新的余数。 计算新余数的输入包括来自一个或多个多个寄存器的数据。
-
89.发明授权System and method for providing a double adder for decimal floating point operations 失效提供用于十进制浮点运算的双加法器的系统和方法公开(公告)号：US07475104B2
公开(公告)日：2009-01-06
申请号：US11054687
申请日：2005-02-09
IPC分类号： G06F7/485
CPC分类号： G06F7/4912 , G06F7/483 , G06F7/507
摘要： A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding digits from the first operand and the second operand. Output from each of the adder blocks includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The calculating is performed during a first clock cycle. The system also includes an intermediate result register for storing the sums of the corresponding digits output from each of the plurality of adder blocks, the storing during the first clock cycle. The system further includes a carry chain for storing the carry out indicator output from each of the plurality of adder blocks, the storing occurring during the first clock cycle. The system further includes an incrementer for adding one to each of the sums stored in the intermediate result register, the incrementing occurring during a second clock cycle. In addition, a mechanism is provided for selecting between each of the sums and the sums incremented by one. The input to the mechanism includes the carry chain. The output includes the final sum of the first operand and the second operand. The selecting occurs during the second clock cycle.
摘要翻译： 用于执行十进制浮点加法的系统。 该系统包括用于输入用于加法运算的第一和第二操作数的输入寄存器。 该系统还包括多个加法器块，每个加法器块从第一操作数和第二操作数计算一个或多个相应数字的和。 来自每个加法器块的输出包括对应数字的和和相应数字的执行指示符。 计算在第一个时钟周期内执行。 该系统还包括中间结果寄存器，用于存储从多个加法器块中的每一个输出的相应数字的和，在第一时钟周期期间存储。 该系统还包括用于存储来自多个加法器块中的每一个的进位指示符输出的进位链，在第一时钟周期期间发生存储。 该系统还包括一个加法器，用于对存储在中间结果寄存器中的每个和加1，在第二时钟周期期间发生递增。 此外，提供了一种机制，用于在每个总和和加1之和之间进行选择。 机构的输入包括进位链。 输出包括第一个操作数和第二个操作数的最后一个和。 选择发生在第二个时钟周期。
-
公开(公告)号：US06829627B2
公开(公告)日：2004-12-07
申请号：US09764595
申请日：2001-01-18
IPC分类号： G06F1500
CPC分类号： G06F7/483 , G06F9/30025 , G06F2207/3812 , G06F2207/382 , G06F2207/3844
摘要： A computer system with a floating point unit (“FPU”) for supporting multiple floating point architectures is provided. The system includes a format converter for converting between the internal data flow format and the architected external data types by multiplexing the exponent and system includes a floating point unit having an internal data-flow according to an internal floating point format for performing floating point operations. The internal format has a number of exponent bits and a number of fraction bits sufficient to support each of the floating point architectures. The format converters the exponent value of each floating point architecture into the internal floating point format so that data operand of any of the floating point architectures point is converted into the internal floating point format for subsequent arithmetic operations, and the result of the operation is converted back into the original floating point architecture for output.
摘要翻译： 提供了一种具有用于支持多个浮点体系结构的浮点单元（“FPU”）的计算机系统。 该系统包括格式转换器，用于通过复用指数来在内部数据流格式和架构外部数据类型之间进行转换，并且系统包括具有根据用于执行浮点运算的内部浮点格式的内部数据流的浮点单元。 内部格式具有多个指数位和足以支持每个浮点体系结构的分数位数。 格式将每个浮点体系结构的指数值转换为内部浮点格式，使任何浮点体系结构点的数据操作数转换为内部浮点格式用于后续算术运算，并将运算结果转换 回到原来的浮点架构进行输出。
-
-
-
-
-
-
-
-
-
搜索结果
94 条记录 (耗时 0.041 秒)