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公开(公告)号：US20090210659A1
公开(公告)日：2009-08-20
申请号：US12032105
申请日：2008-02-15
CPC分类号： G06F9/3861 , G06F9/3017 , G06F9/322 , G06F9/328 , G06F11/0721 , G06F11/0793
摘要： A processor includes a microarchitecture for working around a processing flaw, the microarchitecture including: at least one detector adapted for detecting a predetermined state associated with the processing flaw; and at least one mechanism to modify default processor processing behavior; and upon modification of processing behavior, the processing of an instruction involving the processing flaw can be completed by avoiding the processing flaw.
摘要翻译： 处理器包括用于处理加工缺陷的微架构，所述微体系结构包括：至少一个检测器，适于检测与所述处理缺陷相关联的预定状态; 以及至少一种修改默认处理器处理行为的机制; 并且在修改处理行为时，可以通过避免处理缺陷来完成涉及处理缺陷的指令的处理。
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公开(公告)号：US08443227B2
公开(公告)日：2013-05-14
申请号：US12032105
申请日：2008-02-15
IPC分类号： G06F11/00
CPC分类号： G06F9/3861 , G06F9/3017 , G06F9/322 , G06F9/328 , G06F11/0721 , G06F11/0793
摘要： A processor includes a microarchitecture for working around a processing flaw, the microarchitecture including: at least one detector adapted for detecting a predetermined state associated with the processing flaw; and at least one mechanism to modify default processor processing behavior; and upon modification of processing behavior, the processing of an instruction involving the processing flaw can be completed by avoiding the processing flaw.
摘要翻译： 处理器包括用于处理加工缺陷的微架构，所述微体系结构包括：至少一个检测器，适于检测与所述处理缺陷相关联的预定状态; 以及至少一种修改默认处理器处理行为的机制; 并且在修改处理行为时，可以通过避免处理缺陷来完成涉及处理缺陷的指令的处理。
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3.发明授权公开(公告)号：US08572141B2
公开(公告)日：2013-10-29
申请号：US12051333
申请日：2008-03-19
CPC分类号： G06F7/483 , G06F2207/4911
摘要： A decimal floating point (DFP) unit is used to execute fixed point instructions. Two or more operands are accepted, wherein each operand is in a packed binary coded decimal (BCD) format. Any invalid BCD formats are detected by checking the operands for any invalid BCD codes. It is determined if an exception flag exists and, if so, outputting the flag; it is determined if a condition code exists and, if so, outputting the code. An operation is performed on the two or more operands to generate a result; wherein the operation takes place directly on BCD data, thus using the DFP unit to perform a BCD operation; appending a result sign to the result of the operation; and providing the result of the operation and the appended result sign as a result output in a packed BCD format.
摘要翻译： 使用十进制浮点（DFP）单位执行固定点指令。 接受两个或多个操作数，其中每个操作数都是压缩的二进制编码十进制（BCD）格式。 通过检查任何无效的BCD代码的操作数来检测任何无效的BCD格式。 确定是否存在异常标志，如果是，则输出该标志; 确定条件代码是否存在，如果是，则输出代码。 对两个或更多个操作数执行操作以产生结果; 其中操作直接发生在BCD数据上，因此使用DFP单元执行BCD操作; 将结果符号附加到操作结果; 并提供操作结果和附加结果符号作为输出的压缩BCD格式的结果。
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4.发明申请METHOD, HARDWARE PRODUCT, AND COMPUTER PROGRAM PRODUCT FOR USING A DECIMAL FLOATING POINT UNIT TO EXECUTE FIXED POINT INSTRUCTIONS 有权方法，硬件产品和计算机程序产品，用于使用十进制浮点单元执行固定点说明公开(公告)号：US20090240753A1
公开(公告)日：2009-09-24
申请号：US12051333
申请日：2008-03-19
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F2207/4911
摘要： A decimal floating point (DFP) unit is used to execute fixed point instructions. Two or more operands are accepted, wherein each operand is in a packed binary coded decimal (BCD) format. Any invalid BCD formats are detected by checking the operands for any invalid BCD codes. It is determined if an exception flag exists and, if so, outputting the flag; it is determined if a condition code exists and, if so, outputting the code. An operation is performed on the two or more operands to generate a result; wherein the operation takes place directly on BCD data, thus using the DFP unit to perform a BCD operation; appending a result sign to the result of the operation; and providing the result of the operation and the appended result sign as a result output in a packed BCD format.
摘要翻译： 使用十进制浮点（DFP）单位执行固定点指令。 接受两个或多个操作数，其中每个操作数都是压缩的二进制编码十进制（BCD）格式。 通过检查任何无效的BCD代码的操作数来检测任何无效的BCD格式。 确定是否存在异常标志，如果是，则输出该标志; 确定条件代码是否存在，如果是，则输出代码。 对两个或更多个操作数执行操作以产生结果; 其中操作直接发生在BCD数据上，因此使用DFP单元执行BCD操作; 将结果符号附加到操作结果; 并提供操作结果和附加结果符号作为输出的压缩BCD格式的结果。
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5.发明授权Identifying decimal floating point addition operations that do not require alignment, normalization or rounding 有权识别不需要对齐，归一化或舍入的十进制浮点加法运算公开(公告)号：US08392490B2
公开(公告)日：2013-03-05
申请号：US12032858
申请日：2008-02-18
CPC分类号： G06F7/4912 , G06F7/485
摘要： A method, computer program product and a system for identifying decimal floating point addition operations that guarantee operand alignment and do not require alignment, normalization or rounding are provided. The method includes: receiving an instruction to perform an addition of a first operand and a second operand; extracting a first exponent (EXP) and a first most significant digit (MSD) from the first operand; extracting a second EXP and a second MSD from the second operand; and determining whether alignment between the first operand and the second operand is guaranteed, based on the first EXP, the first MSD, the second EXP and the second MSD.
摘要翻译： 提供一种方法，计算机程序产品和用于识别保证操作数对齐并且不需要对准，归一化或舍入的十进制浮点加法运算的系统。 该方法包括：接收执行第一操作数和第二操作数的相加的指令; 从所述第一操作数提取第一指数（EXP）和第一最高有效数字（MSD）; 从第二操作数提取第二EXP和第二MSD; 以及基于所述第一EXP，所述第一MSD，所述第二EXP和所述第二MSD，确定所述第一操作数与所述第二操作数之间的对准是否得到保证。
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6.发明申请METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR IDENTIFYING DECIMAL FLOATING POINT ADDITION OPERATIONS THAT DO NOT REQUIRE ALIGNMENT, NORMALIZATION OR ROUNDING 有权方法，系统和计算机程序产品，用于识别不需要对齐，正规化或环绕的十进制浮点附加操作公开(公告)号：US20090210472A1
公开(公告)日：2009-08-20
申请号：US12032858
申请日：2008-02-18
IPC分类号： G06F7/485
CPC分类号： G06F7/4912 , G06F7/485
摘要： A method, computer program product and a system for identifying decimal floating point addition operations that guarantee operand alignment and do not require alignment, normalization or rounding are provided. The method includes: receiving an instruction to perform an addition of a first operand and a second operand; extracting a first exponent (EXP) and a first most significant digit (MSD) from the first operand; extracting a second EXP and a second MSD from the second operand; and determining whether alignment between the first operand and the second operand is guaranteed, based on the first EXP, the first MSD, the second EXP and the second MSD.
摘要翻译： 提供一种方法，计算机程序产品和用于识别保证操作数对齐并且不需要对准，归一化或舍入的十进制浮点加法运算的系统。 该方法包括：接收执行第一操作数和第二操作数的相加的指令; 从所述第一操作数提取第一指数（EXP）和第一最高有效数字（MSD）; 从第二操作数提取第二EXP和第二MSD; 以及基于所述第一EXP，所述第一MSD，所述第二EXP和所述第二MSD，确定所述第一操作数与所述第二操作数之间的对准是否得到保证。
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7.发明授权Decimal floating point mechanism and process of multiplication without resultant leading zero detection 失效十进制浮点机制和乘法处理，而没有得到前导零检测公开(公告)号：US08495124B2
公开(公告)日：2013-07-23
申请号：US12821648
申请日：2010-06-23
IPC分类号： G06F7/52
CPC分类号： G06F7/4915 , G06F2207/4911
摘要： A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N−1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product. The corrective final product shifting also incorporates adjustments to the coefficient of the product when the product's exponent is at its extremes and the final product must be brought to be within the precision and range of a given format.
摘要翻译： 具有系数机制而不产生前导零检测（LZD）的计算机中的固定和浮点计算的十进制乘法机制，其假定最终产品的长度为M + N个数字，并且基于该假设执行所有计算。 将被截断的最低有效数字不再存储，而是保留为用于确定结果产品的粘性信息。 一旦产品的计算完成，就使用基于在部分积累期间观察到的关键位的检查的最终检查来确定最终产品是真正的M + N个数字的长度，还是M + N-1个数字。 如果后者是真实的，则采用校正最终产品转换来获得适当的结果。 这消除了用于确定最终产品中有效数字数量的专用前导零检测硬件的需要。 当产品的指数处于极端状态并且最终产品必须在给定格式的精度和范围内时，纠正性最终产品转移也会对产品系数进行调整。
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公开(公告)号：US20110320514A1
公开(公告)日：2011-12-29
申请号：US12822919
申请日：2010-06-24
IPC分类号： G06F7/485
摘要： Binary code decimal (BCD) arithmetic add/subtract operations on two BCD numbers independent of which BCD number is of a greater magnitude include, responsive to the BCD arithmetic add/subtract operation being a subtract operation, performing a BCD arithmetic subtraction operation on a first BCD number and a second BCD number, the first BCD number having a first magnitude and the second BCD number having a second magnitude. The first magnitude is greater than, equal to, or less than the second magnitude. The performing includes: in parallel to a carry generation, partial sums or partial differences of the first and second BCD numbers are computer such that a final result in signed magnitude form is selectable from the partial sums or differences based on carry information without any post processing steps.
摘要翻译： 对于与BCD数量不同的两个BCD号码的二进制码十进制（BCD）算术加法/减法操作包括响应于BCD算术加/减操作作为减法运算，对第一个BCD运算执行BCD运算减法运算 BCD号和第二BCD号，第一BCD号具有第一幅值，第二BCD号具有第二幅值。 第一幅度大于等于或小于第二幅度。 执行包括：与进位生成并行，第一和第二BCD号码的部分和或部分差异是计算机，使得基于携带信息的部分和或差异可以从签名幅度形式中选择最终结果，而不进行任何后处理 脚步。
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9.发明申请公开(公告)号：US20110320512A1
公开(公告)日：2011-12-29
申请号：US12821648
申请日：2010-06-23
CPC分类号： G06F7/4915 , G06F2207/4911
摘要： A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N−1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product. The corrective final product shifting also incorporates adjustments to the coefficient of the product when the product's exponent is at its extremes and the final product must be brought to be within the precision and range of a given format.
摘要翻译： 具有系数机制而不产生前导零检测（LZD）的计算机中的固定和浮点计算的十进制乘法机制，其假设最终产品的长度为M + N个数字，并且基于该假设执行所有计算。 将被截断的最低有效数字不再存储，而是保留为用于确定结果产品的粘性信息。 一旦产品的计算完成，就使用基于在部分积累期间观察到的关键位的检查的最终检查来确定最终产品是真正的M + N个数字的长度，还是M + N-1个数字。 如果后者是真实的，则采用校正最终产品转换来获得适当的结果。 这消除了用于确定最终产品中有效数字数量的专用前导零检测硬件的需要。 当产品的指数处于极端状态并且最终产品必须在给定格式的精度和范围内时，纠正性最终产品转移也会对产品系数进行调整。
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公开(公告)号：US08554822B2
公开(公告)日：2013-10-08
申请号：US12822919
申请日：2010-06-24
IPC分类号： G06F7/494
摘要： Binary code decimal (BCD) arithmetic add/subtract operations on two BCD numbers independent of which BCD number is of a greater magnitude include, responsive to the BCD arithmetic add/subtract operation being a subtract operation, performing a BCD arithmetic subtraction operation on a first BCD number and a second BCD number, the first BCD number having a first magnitude and the second BCD number having a second magnitude. The first magnitude is greater than, equal to, or less than the second magnitude. The performing includes: in parallel to a carry generation, partial sums or partial differences of the first and second BCD numbers are computer such that a final result in signed magnitude form is selectable from the partial sums or differences based on carry information without any post processing steps.
摘要翻译： 对于与BCD数量不同的两个BCD号码的二进制码十进制（BCD）算术加法/减法操作包括响应于BCD算术加/减操作作为减法运算，对第一个BCD运算执行BCD运算减法运算 BCD号和第二BCD号，第一BCD号具有第一幅值，第二BCD号具有第二幅值。 第一幅度大于等于或小于第二幅度。 执行包括：与进位生成并行，第一和第二BCD号码的部分和或部分差异是计算机，使得基于携带信息的部分和或差异可以从签名幅度形式中选择最终结果，而不进行任何后处理 脚步。
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