公开(公告)号：US06859916B1

公开(公告)日：2005-02-22

申请号：US10062995

申请日：2002-01-31

申请人： Steven Teig ,  Andrew Caldwell

发明人： Steven Teig ,  Andrew Caldwell

IPC分类号： G06F17/50 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/528 ,  G06F17/5068 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provide a first set of vias that have a diamond shape and a second set of vias that have a rectangular shape. In some embodiments, a via can also be formed by a diamond contact and a rectangular contact. The diamond contact has four sides. In the embodiments described below, all four sides of a diamond via contact have equal sides. However, in other embodiments, a via contact can be in shape of a diamond with a pair of sides that are longer than the other pair of sides. Similarly, in the embodiments described below, the rectangular via contacts are squares with four equal sides. However, in other embodiments, the length and width of a rectangular via contact can differ. Some embodiments of the invention provide interconnect lines that have non-rectangular ends. In some embodiments, the interconnect-line ends are partial octagons, hexagons, and/or circles. Also, some embodiments provide Steiner points that are not rectangular. In some embodiments, the Steiner points are octagonal, hexagonal, or circles.

摘要翻译： 本发明的一些实施例提供不具有四边形形状的通孔。 在一些实施例中，一些或所有通孔的形状为非四边形多边形，例如八边形和六边形。 在一些实施例中，一些或所有通孔具有圆形形状。 一些实施例提供具有菱形形状的第一组通孔和具有矩形形状的第二组通孔。 在一些实施例中，也可以通过金刚石触点和矩形触点形成通孔。 钻石接触有四面。 在下面描述的实施例中，钻石经过接触的所有四个侧面具有相等的边。 然而，在其他实施例中，通孔接触可以是具有比另一对侧长的一对侧面的菱形的形状。 类似地，在下面描述的实施例中，矩形通孔触点是具有四个相等边的正方形。 然而，在其他实施例中，矩形通孔接触件的长度和宽度可以不同。 本发明的一些实施例提供具有非矩形端部的互连线。 在一些实施例中，互连线端部是部分八边形，六边形和/或圆形。 而且，一些实施例提供了不是矩形的Steiner点。 在一些实施例中，Steiner点是八边形，六边形或圆形。

公开(公告)号：US08726213B2

公开(公告)日：2014-05-13

申请号：US12414660

申请日：2009-03-30

申请人： Andrew Caldwell ,  Herman Schmit ,  Steven Teig

发明人： Andrew Caldwell ,  Herman Schmit ,  Steven Teig

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/505 ,  H03K19/1737 ,  H03K19/177

摘要： Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.

摘要翻译： 本发明的一些实施例提供了可配置的集成电路（“IC”）。 可配置IC包括一组多路复用器，每组具有一组输入端子，一组输出端子和一组选择端子。 该组多路复用器包括一组多路复用器，其中组中的每个多路复用器的至少一个输入端是永久反相输入端。 在可配置IC的操作期间的至少一组周期期间，使用多路复用器组中的多个多路复用器来实现特定功能。

公开(公告)号：US08664974B2

公开(公告)日：2014-03-04

申请号：US13011840

申请日：2011-01-21

申请人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

发明人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

IPC分类号： H03K19/173 ,  H01L25/00 ,  G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17776

摘要： A reconfigurable integrated circuit (“IC”) that has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

摘要翻译： 具有几个可重新配置电路的可重构集成电路（“IC”），每个可配置电路在几个配置周期中具有多种配置。 可重新配置的电路包括几个延时可重构电路。 在IC的操作期间，每个特定的时间延长的可重新配置电路在至少两个连续周期内保持其配置中的至少一个，以便允许信号传播通过包含特定延时电路的信号路径， 在期望的时间内。

公开(公告)号：US08555218B2

公开(公告)日：2013-10-08

申请号：US12994453

申请日：2009-05-22

申请人： Andrew Caldwell ,  Steven Teig

发明人： Andrew Caldwell ,  Steven Teig

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： An abstract decision module primitive for placement within a logical representation (i.e., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information. The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module as additional constraint information is identified.

公开(公告)号：US08458629B2

公开(公告)日：2013-06-04

申请号：US12954575

申请日：2010-11-24

申请人： Andrew Caldwell ,  Steven Teig

发明人： Andrew Caldwell ,  Steven Teig

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F9/455 ,  G06F11/22

CPC分类号： G06F17/5045 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： An abstract decision module primitive for placement within a logical representation (i.e., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information. The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module as additional constraint information is identified.

摘要翻译： 描述了用于放置在电路设计的逻辑表示（即，网表中）的抽象决策模块原语。 决策模块原语接收网表的给定功能或段的输入替代解决方案。 替代解决方案包括功能等同，但在网表的功能或段的结构上不同的实现。 所述决策模块基元可选择在连接到所述网表之一的输入之间，以基于约束信息为所述网表提供完整的功能定义。 当在设计过程的各个阶段确定附加约束信息时，可以更新决策模块的所选择的输入。 此外，当识别出额外的约束信息时，可以向决策模块的输入添加和/或从其中删除网表的给定功能或段的替代解决方案。

公开(公告)号：US20120176155A1

公开(公告)日：2012-07-12

申请号：US13426592

申请日：2012-03-21

申请人： Scott J. Weber ,  Christopher D. Ebeling ,  Andrew Caldwell ,  Steven Teig ,  Timothy J. Callahan ,  Hung Q. Nguyen ,  Shangzhi Sun ,  Shilpa V. Yeole

发明人： Scott J. Weber ,  Christopher D. Ebeling ,  Andrew Caldwell ,  Steven Teig ,  Timothy J. Callahan ,  Hung Q. Nguyen ,  Shangzhi Sun ,  Shilpa V. Yeole

IPC分类号： H03K19/173 ,  G06F17/50

CPC分类号： H03K19/17736 ,  G06F17/505

摘要： A novel method for designing an integrated circuit (“IC”) by resealing an original set of circuits in a design of the IC is disclosed. The original set of circuits to be resealed includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a resealed set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the resealed set of circuits.

摘要翻译： 公开了一种通过在IC的设计中重新密封原始电路组来设计集成电路（“IC”）的新颖方法。 要重新密封的原始电路组包括顺序节点，组合节点和互连。 每个顺序节点与时钟的相位相关联。 该方法产生包括电路的多个复制集合的重新密封的电路组。 每个电路副本集包括与原始电路组中的节点和互连相同的顺序节点，组合节点和互连。 每个顺序节点与时钟的相位相关联，时钟的相位是原始集合中其对应的顺序元素的相位的一小部分。 该方法将每个电路副本中的节点连接到另一个副本集中的逻辑等效节点。 该方法用重新封装的电路组替换原始电路组。

公开(公告)号：US08166435B2

公开(公告)日：2012-04-24

申请号：US12215697

申请日：2008-06-26

申请人： Steven Teig ,  Andrew Caldwell

发明人： Steven Teig ,  Andrew Caldwell

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5054 ,  G06F2217/84 ,  H03K19/1731 ,  H03K19/17748

摘要： Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs.

摘要翻译： 一些实施例提供了一种识别用于在集成电路（IC）的几个可重新配置的电路上定位多个可配置操作的第一物理设计解决方案的方法。 该方法识别用于将可配置操作定位在可配置电路上的第二物理设计解决方案。 所识别的物理设计解决方案之一具有一个可重构电路在至少两个重新配置周期中执行特定的可配置操作，而另一个识别的解决方案没有一个可重配置电路在两个重新配置周期中执行特定的可配置操作。 该方法花费第一和第二物理设计解决方案。 该方法基于成本选择两种物理设计方案之一。

公开(公告)号：US08112468B1

公开(公告)日：2012-02-07

申请号：US11754262

申请日：2007-05-25

申请人： Jason Redgrave ,  Andrew Caldwell ,  Steven Teig

发明人： Jason Redgrave ,  Andrew Caldwell ,  Steven Teig

IPC分类号： G06F7/52

CPC分类号： G06F17/504 ,  H03K19/1733

摘要： Some embodiments provide a method of performing a mathematical operation on a set of operands. The mathematical operation includes several sub-operations. The method examines several bits of at least one operand at a time and depending on the value of these bits, reconfigures a single logic circuit to perform one of the sub-operations to generate a partial result of the mathematical operation. In some embodiments, the logic circuit is reconfigured by receiving a first set of configuration data that cause the logic circuit to reconfigure to perform a first sub-operation operation and a second set of configuration data that cause the logic circuit to reconfigure to perform a second sub-operation. In some embodiments, the logic circuit receives different inputs based on the value of the bits being examined. In some embodiments, the mathematical operation is multiplication and the sub-operations are addition and subtraction.

摘要翻译： 一些实施例提供了对一组操作数执行数学运算的方法。 数学运算包括几个子操作。 该方法一次检查至少一个操作数的几位，并且根据这些位的值，重新配置单个逻辑电路以执行子操作之一以产生数学运算的部分结果。 在一些实施例中，通过接收第一组配置数据来重新配置逻辑电路，所述第一组配置数据使逻辑电路重新配置以执行第一子操作操作和第二组配置数据，使得逻辑电路重新配置以执行第二 子操作。 在一些实施例中，逻辑电路基于所检查的位的值来接收不同的输入。 在一些实施例中，数学运算是乘法运算，子运算是加法和减法运算。

公开(公告)号：US08069425B2

公开(公告)日：2011-11-29

申请号：US11769680

申请日：2007-06-27

申请人： Brad Hutchings ,  Andrew Caldwell ,  Steven Teig

发明人： Brad Hutchings ,  Andrew Caldwell ,  Steven Teig

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5045 ,  G06F2217/84

摘要： Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit elements(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.

摘要翻译： 一些实施例提供了在可配置集成电路（IC）中监视用户设计的实现的方法。 该方法接收IC的用户设计，并优化用户设计以产生第二IC设计。 优化导致消除电路元件。 该方法定义了可配置IC的第二个IC设计，并为消除的电路元件生成输出数据，以便监视用户设计。

公开(公告)号：US20110181317A1

公开(公告)日：2011-07-28

申请号：US13011840

申请日：2011-01-21

申请人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

发明人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

IPC分类号： H03K19/173

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17776

摘要： Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit. The method then maintains a configuration of the particular reconfigurable circuit constant over at least two contiguous reconfiguration cycles in order to reduce signal delay through the signal path and thereby satisfy the timing constraint.

摘要翻译： 一些实施例提供可重构集成电路（“IC”）。 该IC具有几个可重新配置电路，每个具有几个配置周期的配置。 可重新配置的电路包括几个延时可重构电路。 在IC的操作期间，每个特定的时间延长的可重新配置电路在至少两个连续周期内保持其配置中的至少一个，以便允许信号传播通过包含特定延时电路的信号路径， 在期望的时间内。 一些实施例提供了一种设计可重配置IC的方法，该可重配置IC具有若干可重构电路，每个可重新配置电路具有若干配置并在几个重新配置周期中操作。 该方法识别通过IC的不符合定时约束的信号路径。 信号路径包括几个电路，其中之一是特定的可重新配置电路。 该方法然后在至少两个连续的重新配置周期上保持特定可重新配置电路的配置不变，以减少通过信号路径的信号延迟，从而满足定时约束。