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    RESCALING
    1.
    发明申请
    RESCALING 有权
    重视

    公开(公告)号：US20120176155A1

    公开(公告)日：2012-07-12

    申请号：US13426592

    申请日：2012-03-21

    申请人： Scott J. Weber ,  Christopher D. Ebeling ,  Andrew Caldwell ,  Steven Teig ,  Timothy J. Callahan ,  Hung Q. Nguyen ,  Shangzhi Sun ,  Shilpa V. Yeole

    发明人： Scott J. Weber ,  Christopher D. Ebeling ,  Andrew Caldwell ,  Steven Teig ,  Timothy J. Callahan ,  Hung Q. Nguyen ,  Shangzhi Sun ,  Shilpa V. Yeole

    IPC分类号： H03K19/173 ,  G06F17/50

    CPC分类号： H03K19/17736 ,  G06F17/505

    摘要： A novel method for designing an integrated circuit (“IC”) by resealing an original set of circuits in a design of the IC is disclosed. The original set of circuits to be resealed includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a resealed set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the resealed set of circuits.

    摘要翻译： 公开了一种通过在IC的设计中重新密封原始电路组来设计集成电路（“IC”）的新颖方法。 要重新密封的原始电路组包括顺序节点，组合节点和互连。 每个顺序节点与时钟的相位相关联。 该方法产生包括电路的多个复制集合的重新密封的电路组。 每个电路副本集包括与原始电路组中的节点和互连相同的顺序节点，组合节点和互连。 每个顺序节点与时钟的相位相关联，时钟的相位是原始集合中其对应的顺序元素的相位的一小部分。 该方法将每个电路副本中的节点连接到另一个副本集中的逻辑等效节点。 该方法用重新封装的电路组替换原始电路组。

    Configurable storage elements
    2.
    发明授权
    Configurable storage elements 有权
    可配置的存储元素

    公开(公告)号：US09148151B2

    公开(公告)日：2015-09-29

    申请号：US13549405

    申请日：2012-07-13

    申请人： Steven Teig ,  Christopher D. Ebeling ,  Martin Voogel ,  Andrew Caldwell

    发明人： Steven Teig ,  Christopher D. Ebeling ,  Martin Voogel ,  Andrew Caldwell

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1736 ,  H03K19/17744

    摘要： A low power sub-cycle reconfigurable conduit is provided. The low power reconfigurable conduit is a clocked storage element that consumes less power when performing low-throughput operations that do not require sub-cycle rate. The low power conduit includes a first configurable routing multiplexer that is reconfigurable to select one of several inputs at a first clock rate. The low power conduit also includes an array of storage elements for storing output data from the configurable routing multiplexer at the first clock rate. Each storage element in the array of storage elements operate at a second clock rate that is slower than the first clock rate. Each storage element receives a different phase of a clock that operates at the second clock rate. The low power conduit also includes a second configurable routing multiplexer that is reconfigurable to select from the array of storage elements at the first clock rate.

    摘要翻译： 提供了一个低功率子循环可重新配置的管道。 低功率可重新配置的管道是一种时钟存储元件，当执行不需要子周期速率的低通量操作时，可以消耗较少的功耗。 低功率管道包括第一可配置路由多路复用器，其可重新配置以以第一时钟速率选择多个输入中的一个。 低功率管道还包括用于以第一时钟速率存储来自可配置路由多路复用器的输出数据的存储元件阵列。 存储元件阵列中的每个存储元件以比第一时钟速率慢的第二时钟速率工作。 每个存储元件接收以第二时钟速率工作的时钟的不同相位。 低功率管道还包括可配置的第二可配置路由多路复用器，以便以第一时钟速率从存储元件阵列中进行选择。

    Queuing and aligning data
    3.
    发明授权
    Queuing and aligning data 有权
    排队和对齐数据

    公开(公告)号：US07254691B1

    公开(公告)日：2007-08-07

    申请号：US11072106

    申请日：2005-03-04

    申请人： Christopher D. Ebeling

    发明人： Christopher D. Ebeling

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0646

    摘要： Queuing and ordering data is described. Data is stored or queued in concatenated memories where each of the memories has a respective set of data out ports. An aligner having multiplexers arranged in a lane sequence are coupled to each set of the data out ports. A virtual-to-physical address translator is configured to translate a virtual address to provide physical addresses and select signals, where the physical addresses are locations of at least a portion of data words of a cell stored in the concatenated memories in successive order. The multiplexers are coupled to receive the select signals as control select signaling to align the at least one data word obtained from each of the concatenated memories for lane aligned output from the aligner.

    摘要翻译： 描述排队和排序数据。 数据被存储或排队在连接的存储器中，其中每个存储器具有相应的一组数据输出端口。 具有布置在车道序列中的多路复用器的对准器被耦合到每组数据输出端口。 虚拟到物理地址转换器被配置为转换虚拟地址以提供物理地址和选择信号，其中物理地址是连续顺序存储在级联存储器中的单元的至少一部分数据字的位置。 多路复用器被耦合以接收选择信号作为控制选择信号，以对准从每个级联存储器获得的至少一个数据字，用于对准器的车道对准输出。

    Windowing circuit for aligning data and clock signals
    5.
    发明授权
    Windowing circuit for aligning data and clock signals 有权
    用于对准数据和时钟信号的窗口电路

    公开(公告)号：US06864715B1

    公开(公告)日：2005-03-08

    申请号：US10377461

    申请日：2003-02-27

    申请人： Trevor J. Bauer ,  Steven P. Young ,  Christopher D. Ebeling ,  Jason R. Bergendahl ,  Arthur J. Behiel

    发明人： Trevor J. Bauer ,  Steven P. Young ,  Christopher D. Ebeling ,  Jason R. Bergendahl ,  Arthur J. Behiel

    IPC分类号： G06F1/025 ,  H03K5/135 ,  H03K19/177 ,  H04L7/00 ,  G06F7/38 ,  H03D3/24 ,  H03K19/173

    CPC分类号： H03K19/17764 ,  G06F1/025 ,  H03K5/135 ,  H03K19/1774 ,  H04L7/0004 ,  H04L7/0037 ,  H04L7/0041

    摘要： Described are circuits and methods for aligning data and clock signals. Circuits in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.

    摘要翻译： 描述了用于对准数据和时钟信号的电路和方法。 根据一些实施例的电路将输入数据分成三个不同定时的数据信号：早期信号，中间信号和后期信号。 三个数据信号的定时可以相对于时钟信号共同移动。 此外，可以调整三个信号之间的时间间隔，使得早期和晚期信号限定包围中间信号的窗口。 三个信号相对于时钟边沿对齐，以使中间数据信号在时钟边沿居中。 可以监视早期和晚期信号以识别时钟和数据信号的相对时序的变化。 一些实施例自动改变数据和/或时钟信号的定时，以使中间数据信号以时钟边缘为中心。

    FIFO memory including a comparator circuit for determining full/empty conditions using mode control and carry chain multiplexers
    6.
    发明授权
    FIFO memory including a comparator circuit for determining full/empty conditions using mode control and carry chain multiplexers 失效
    FIFO存储器包括用于使用模式控制和携带链多路复用器来确定满/空条件的比较器电路

    公开(公告)号：US06405269B1

    公开(公告)日：2002-06-11

    申请号：US09568556

    申请日：2000-05-09

    申请人： Nicolas J. Camilleri ,  Christopher D. Ebeling

    发明人： Nicolas J. Camilleri ,  Christopher D. Ebeling

    IPC分类号： G06F1200

    CPC分类号： G06F5/14 ,  G06F5/12 ,  G06F2205/102 ,  G06F2205/126 ,  G11C19/287

    摘要： A comparator circuit for detecting full and empty conditions in a first-in first-out (FIFO) memory system. The comparator circuit includes two-input logic circuits for comparing selected read and write addresses. An almost-empty condition is detected by comparing a next-to-be-used read address value with a currently-used write address value. When these address values are equal, high logic signals are passed by a set of mode control multiplexers to the select terminals of a series of carry chain multiplexers, thereby causing a high logic value to be transmitted to a data input terminal of a first register. The first register latches the high logic signal at the next rising edge of the read clock signal, thereby generating a high EMPTY control signal immediately after a final data value is read from the memory. The high EMPTY control signal causes the mode control multiplexers to pass logic signals generated by comparing a current read address value and a current write address value, which are equal when the memory is in the empty condition. The full condition is determined in a similar fashion, using a second carry chain to transmit logic signals related to both an almost-full and the full condition.

    摘要翻译： 一种用于检测先进先出（FIFO）存储器系统中的全部和空的条件的比较器电路。 比较器电路包括用于比较选择的读取和写入地址的双输入逻辑电路。 通过将下一个待使用的读取地址值与当前使用的写入地址值进行比较来检测几乎为空的条件。 当这些地址值相等时，高逻辑信号由一组模式控制多路复用器传递给一系列进位链多路复用器的选择端，从而使高逻辑值被发送到第一寄存器的数据输入端。 第一个寄存器在读取时钟信号的下一个上升沿锁存高逻辑信号，从而在从存储器读取最终数据值之后立即产生高EMPTY控制信号。 高EMPTY控制信号使得模式控制多路复用器通过比较当存储器处于空状态时相等的当前读地址值和当前写地址值而产生的逻辑信号。 以类似的方式确定完整状态，使用第二进位链发送与几乎满和完全状态相关的逻辑信号。

    Rescaling
    7.
    发明授权
    Rescaling 有权
    重新调整

    公开(公告)号：US08650514B2

    公开(公告)日：2014-02-11

    申请号：US13426592

    申请日：2012-03-21

    申请人： Scott J. Weber ,  Christopher D. Ebeling ,  Andrew Caldwell ,  Steven Teig ,  Timothy J. Callahan ,  Hung Q. Nguyen ,  Shangzhi Sun ,  Shilpa V. Yeole

    发明人： Scott J. Weber ,  Christopher D. Ebeling ,  Andrew Caldwell ,  Steven Teig ,  Timothy J. Callahan ,  Hung Q. Nguyen ,  Shangzhi Sun ,  Shilpa V. Yeole

    IPC分类号： G06F17/50

    CPC分类号： H03K19/17736 ,  G06F17/505

    摘要： A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

    摘要翻译： 公开了一种通过在IC的设计中重新缩放原始电路组来设计集成电路（“IC”）的新颖方法。 要重新定标的原始电路组包括顺序节点，组合节点和互连。 每个顺序节点与时钟的相位相关联。 该方法产生包括电路的多个复制集合的重新定标的电路集合。 每个电路副本集包括与原始电路组中的节点和互连相同的顺序节点，组合节点和互连。 每个顺序节点与时钟的相位相关联，时钟的相位是原始集合中其对应的顺序元素的相位的一小部分。 该方法将每个电路副本中的节点连接到另一个副本集中的逻辑等效节点。 该方法用重新定标的电路组替换原始电路组。

    Method and apparatus for appliance installation and leveling
    8.
    发明授权
    Method and apparatus for appliance installation and leveling 有权
    用于电器安装和调平的方法和装置

    公开(公告)号：US06871379B2

    公开(公告)日：2005-03-29

    申请号：US10261808

    申请日：2002-10-01

    申请人： Christopher D. Ebeling ,  Brian D. Wylie

    发明人： Christopher D. Ebeling ,  Brian D. Wylie

    IPC分类号： B60B33/06 ,  B60B33/04

    CPC分类号： B60B33/0018 ,  B60B33/0028 ,  B60B33/0042 ,  B60B33/0049 ,  B60B33/0063 ,  B60B33/04 ,  F25D2323/0011 ,  Y10T16/182 ,  Y10T16/193

    摘要： A method and apparatus for appliance installation and leveling using a leveling caster. The leveling caster includes a top shelf connected to wheels by a scissors type structure. The height of the scissors type structure can be adjusted using an adjustment bolt from the front of the appliance, without requiring access to the rear of the appliance. The leveling caster is adjustable over a wide range of heights, is strong enough to bear heavy appliances, and allows height adjustment while minimizing incidental horizontal motion.

    摘要翻译： 一种使用平整脚轮的电器安装和调平的方法和装置。 平整脚轮包括通过剪刀式结构连接到车轮的顶架。 剪刀式结构的高度可以使用设备前部的调节螺栓调节，而不需要进入设备的后部。 调平脚轮在高度范围内可调，强度足以承受重型器具，并允许高度调节，同时尽量减少偶然的水平运动。

    FIFO memory system and method with improved determination of full and empty conditions and amount of data stored
    9.
    发明授权
    FIFO memory system and method with improved determination of full and empty conditions and amount of data stored 有权
    FIFO存储器系统和方法具有改善的确定的全部和空的条件和存储的数据量

    公开(公告)号：US06434642B1

    公开(公告)日：2002-08-13

    申请号：US09414987

    申请日：1999-10-07

    申请人： Nicolas J. Camilleri ,  Peter H. Alfke ,  Christopher D. Ebeling

    发明人： Nicolas J. Camilleri ,  Peter H. Alfke ,  Christopher D. Ebeling

    IPC分类号： G06F1200

    CPC分类号： G06F5/14 ,  G06F5/12 ,  G06F2205/102 ,  G06F2205/126 ,  G11C19/287

    摘要： A structure and method for operating an asynchronous first in, first out (FIFO) memory system in which the full or empty condition of the memory is determined by comparing a currently-generated write address with a currently-generated read address and a next-to-be-used read address. The current write address and current read address are transmitted from a write address counter and a read address counter, respectively, to a flag control circuit. The flag control circuit includes registers for storing Gray-code versions of the current write address, the current read address, and the next-to-be-used read address, which is determined from the current read address. The flag control circuit generates intermediate ALMOST_EMPTY and ALMOST_FULL signals when the FIFO memory is one data value from being “empty” and “full”, respectively. These intermediate signals are used to generate FULL and EMPTY control signals immediately after the FIFO memory enters a “full” or “empty” condition. A status circuit re-synchronizes a binary read address to the write clock signal, then subtracts the write-synchronized read address from the binary write address to accurately determine the amount of data in the FIFO memory.

    摘要翻译： 一种用于操作异步先进先出（FIFO）存储器系统的结构和方法，其中通过将当前生成的写地址与当前生成的读地址进行比较来确定存储器的全状态或空状态， 使用的读取地址。 当前写入地址和当前读取地址分别从写入地址计数器和读取地址计数器发送到标志控制电路。 标志控制电路包括用于存储从当前读取地址确定的当前写入地址，当前读取地址和下一个要使用的读取地址的格雷码版本的寄存器。 当FIFO存储器分别为“空”和“满”的一个数据值时，标志控制电路产生中间ALMOST_EMPTY和ALMOST_FULL信号。 这些中间信号用于在FIFO存储器进入“满”或“空”状态之后立即产生FULL和EMPTY控制信号。 状态电路将二进制读取地址重新同步到写入时钟信号，然后从二进制写入地址中减去写入同步的读取地址，以精确地确定FIFO存储器中的数据量。