公开(公告)号：US20220037498A1

公开(公告)日：2022-02-03

申请号：US17336599

申请日：2021-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chen-Ping Chen ,  Hsiaowen Lee ,  Chih-Han Lin

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/8238

Abstract: In an embodiment, a device includes: an isolation region; nanostructures protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.

公开(公告)号：US20210367059A1

公开(公告)日：2021-11-25

申请号：US17069460

申请日：2020-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Pei-Hsiu Wu ,  Chih Ping Wang ,  Chih-Han Lin ,  Jr-Jung Lin ,  Yun Ting Chou ,  Chen-Yu Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/285 ,  H01L21/311

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.

公开(公告)号：US20210351281A1

公开(公告)日：2021-11-11

申请号：US16867158

申请日：2020-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234

Abstract: A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper portion of the dummy gate electrode, and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. A third etching process is then performed to etch the lower portion of the dummy gate electrode using the protection layer as an etching mask. The dummy gate electrode is tapered by the third etching process. The protection layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode.

公开(公告)号：US20210242093A1

公开(公告)日：2021-08-05

申请号：US16871514

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66

Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

公开(公告)号：US20210126110A1

公开(公告)日：2021-04-29

申请号：US16870429

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/06 ,  H01L21/027 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L27/088

Abstract: A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second gate dielectric of the first dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

公开(公告)号：US20210126109A1

公开(公告)日：2021-04-29

申请号：US16867867

申请日：2020-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.