公开(公告)号：US20110014781A1

公开(公告)日：2011-01-20

申请号：US12837025

申请日：2010-07-15

申请人： Hiroshi Itokawa ,  Ichiro Mizushima

发明人： Hiroshi Itokawa ,  Ichiro Mizushima

IPC分类号： H01L21/20

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02636 ,  H01L21/02667

摘要： According to one embodiment, a method of fabricating a semiconductor device includes forming a first insulator on a semiconductor substrate, forming a first groove on the insulator to expose at least a part of the semiconductor substrate at a bottom of the first groove, forming a first embedding film including at least germanium in the groove, melting the first embedding film by heat treatment, and crystallizing the first embedding film being melted to a single-crystalline film using the semiconductor substrate as a seed.

摘要翻译： 根据一个实施例，制造半导体器件的方法包括在半导体衬底上形成第一绝缘体，在绝缘体上形成第一凹槽，以在第一凹槽的底部露出半导体衬底的至少一部分，形成第一 将至少含有锗的包埋膜通过热处理熔化，并且使用半导体基板作为种子将第一埋层膜熔化成单晶膜。

公开(公告)号：US20100171164A1

公开(公告)日：2010-07-08

申请号：US12659703

申请日：2010-03-17

申请人： Yoshio Ozawa ,  Ichiro Mizushima ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi

发明人： Yoshio Ozawa ,  Ichiro Mizushima ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material.

摘要翻译： 一种非易失性半导体存储器件，包括具有半导体层和设置在其表面上的绝缘材料的半导体衬底，绝缘材料的表面被半导体层覆盖，并且设置在半导体层上的多个存储单元，存储器 电池包括通过覆盖半导体层的表面而提供的第一电介质膜，设置在绝缘材料上方和第一电介质膜上的多个电荷存储层，设置在每个电荷存储层上的多个第二电介质膜，多个 设置在每个第二电介质膜上的导电层，以及杂质扩散层，其部分或整体形成在绝缘材料的至少上方和半导体层的内部，并且其底端的至少一部分由绝缘体的上表面 材料。

公开(公告)号：US07651930B2

公开(公告)日：2010-01-26

申请号：US12146802

申请日：2008-06-26

申请人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

发明人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

IPC分类号： H01L21/20

CPC分类号： H01L27/115 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203 ,  H01L29/66825

摘要： A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.

摘要翻译： 一种制造半导体存储装置的方法包括在形成在硅衬底上的绝缘膜中的多个位置提供开口部分，然后在其中形成开口部分的绝缘膜上形成非晶硅膜，并且在 开口部。 然后，形成沟槽，将相邻的开口部之间的中点附近的非晶硅膜分割成一个开口部侧的一部分和另一个开口部侧的一部分。 接着，对其中形成沟槽的非晶硅膜进行退火并进行固相结晶以形成具有用作晶种的开口部分的单晶，从而形成硅单晶层。 然后，在硅单晶层上形成存储单元阵列。

公开(公告)号：US07420249B2

公开(公告)日：2008-09-02

申请号：US11849682

申请日：2007-09-04

申请人： Tsutomu Sato ,  Hajime Nagano ,  Ichiro Mizushima ,  Takashi Yamada ,  Yuso Udo ,  Shinichi Nitta

发明人： Tsutomu Sato ,  Hajime Nagano ,  Ichiro Mizushima ,  Takashi Yamada ,  Yuso Udo ,  Shinichi Nitta

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/764 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/10897 ,  H01L27/1203 ,  H01L27/1207

摘要： A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insulating film and a cavity, and a third semiconductor layer surrounding the second semiconductor layer, the third semiconductor layer being formed on the semiconductor substrate.

摘要翻译： 一种半导体器件，包括形成在半导体衬底上的第一半导体层，围绕第一半导体层的第二半导体层，在半导体衬底上形成有绝缘膜和空腔中的一个的第二半导体层和围绕 所述第二半导体层，所述第三半导体层形成在所述半导体衬底上。

公开(公告)号：US07372086B2

公开(公告)日：2008-05-13

申请号：US10820182

申请日：2004-04-08

申请人： Tsutomu Sato ,  Ichiro Mizushima

发明人： Tsutomu Sato ,  Ichiro Mizushima

IPC分类号： H01L29/78

CPC分类号： H01L29/78696 ,  H01L21/3247 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78639 ,  H01L29/78648 ,  H01L29/78654

摘要： A semiconductor device comprises a semiconductor substrate, a MOSFET including a double gate structure provided on the semiconductor substrate, and an isolation region for isolating the MOSFET from other elements comprising a trench provided on the surface of the semiconductor substrate and an insulator provided in the trench, a part of the isolation region in the trench around the MOSFET having a bottom deeper than other part of the isolation region.

摘要翻译： 半导体器件包括半导体衬底，包括设置在半导体衬底上的双栅极结构的MOSFET和用于将MOSFET与其他元件隔离的隔离区，该隔离区包括设置在半导体衬底的表面上的沟槽和设置在沟槽中的绝缘体 在MOSFET周围的沟槽中的隔离区域的一部分具有比隔离区域的其它部分更深的底部。

公开(公告)号：US07358198B2

公开(公告)日：2008-04-15

申请号：US11250439

申请日：2005-10-17

申请人： Nobutoshi Aoki ,  Koichi Kato ,  Katsuyuki Sekine ,  Ichiro Mizushima

发明人： Nobutoshi Aoki ,  Koichi Kato ,  Katsuyuki Sekine ,  Ichiro Mizushima

IPC分类号： H01L21/31

CPC分类号： H01L21/28202 ,  H01L29/513 ,  H01L29/518

摘要： A method is provided with: arranging nitrogen atoms on a surface of a silicon substrate; performing a heat treatment in a hydrogen atmosphere so that the nitrogen atoms and silicon atoms existing on the surface of the silicon substrate are brought into a three-coordinate bond state; and forming a silicon oxide film on the silicon substrate with the three-coordinate bond state of nitrogen atoms and the silicon atoms being maintained.

摘要翻译： 提供了一种方法：在硅衬底的表面上排列氮原子; 在氢气氛中进行热处理，使得存在于硅衬底表面上的氮原子和硅原子处于三配位键状态; 并且在硅衬底上形成具有氮原子的三配位键状态并保持硅原子的氧化硅膜。

公开(公告)号：US20080003771A1

公开(公告)日：2008-01-03

申请号：US11812490

申请日：2007-06-19

申请人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

发明人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

IPC分类号： H01L21/764

CPC分类号： H01L27/10805 ,  B82Y20/00 ,  G02B6/122 ,  G02B6/1225 ,  G02B2006/12097 ,  H01L21/3247 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78639

摘要： To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

摘要翻译： 通过在半导体衬底的表面上二维地形成沟槽，然后对半导体衬底进行热处理，将多个沟槽改变为一个平坦的空间。

公开(公告)号：US07187035B2

公开(公告)日：2007-03-06

申请号：US10237206

申请日：2002-09-09

申请人： Hajime Nagano ,  Takashi Yamada ,  Tsutomu Sato ,  Ichiro Mizushima ,  Hisato Oyamatsu

发明人： Hajime Nagano ,  Takashi Yamada ,  Tsutomu Sato ,  Ichiro Mizushima ,  Hisato Oyamatsu

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A method of manufacturing a semiconductor device substrate is disclosed, which comprises forming a mask layer patterned on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer deposited thinner on the semiconductor substrate than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.

摘要翻译： 公开了一种制造半导体器件衬底的方法，其包括通过电绝缘层形成在半导体层与半导体衬底的表面绝缘的图案化的掩模层，根据掩模层的图案蚀刻半导体层以形成 导通绝缘层的沟槽，蚀刻比半导体衬底更薄的保护层比绝缘层的厚度形成覆盖沟槽侧表面的侧壁保护膜，从绝缘层的底表面蚀刻绝缘层 沟槽到半导体衬底; 以及从蚀刻绝缘层而暴露的半导体衬底的表面生长单晶层。

公开(公告)号：US07148543B2

公开(公告)日：2006-12-12

申请号：US10828337

申请日：2004-04-21

申请人： Takashi Yamada ,  Hajime Nagano ,  Ichiro Mizushima ,  Tsutomu Sato ,  Hisato Oyamatsu ,  Shinichi Nitta

发明人： Takashi Yamada ,  Hajime Nagano ,  Ichiro Mizushima ,  Tsutomu Sato ,  Hisato Oyamatsu ,  Shinichi Nitta

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L29/00 ,  H01L29/04 ,  H01L29/06

CPC分类号： H01L27/10894 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

摘要翻译： 半导体芯片包括基底基板，在基底基板的一部分上具有体积生长层的体器件区域，在基底基板上具有埋入绝缘体的SOI器件区域和埋入绝缘体上的硅层，以及边界层 位于体器件区域和SOI器件区域之间的边界处。 本体装置区域具有第一装置制造表面，其中大块装置位于本体生长层上。 SOI器件区域具有第二器件制造表面，其中SOI器件位于硅层上。 第一和第二装置制造表面被定位在基本均匀的水平。

公开(公告)号：US20060234478A1

公开(公告)日：2006-10-19

申请号：US11455735

申请日：2006-06-20

申请人： Hajime Nagano ,  Takashi Yamada ,  Tsutomu Sato ,  Ichiro Mizushima ,  Hisato Oyamatsu

发明人： Hajime Nagano ,  Takashi Yamada ,  Tsutomu Sato ,  Ichiro Mizushima ,  Hisato Oyamatsu

IPC分类号： H01L21/36

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A method of manufacturing a semiconductor device substrate includes forming a mask layer pattern on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer on the semiconductor substrate having a thickness less than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.

摘要翻译： 一种制造半导体器件基板的方法包括：通过电绝缘层在与半导体衬底的表面绝缘的半导体层上形成掩模层图案，根据掩模层的图案蚀刻半导体层，形成通向 绝缘层，蚀刻具有小于绝缘层厚度的厚度的半导体衬底上的保护层，以形成覆盖沟槽侧表面的侧壁保护膜，从沟槽的底表面蚀刻绝缘层至 半导体衬底; 以及从蚀刻绝缘层而暴露的半导体衬底的表面生长单晶层。