公开(公告)号：US4608464A

公开(公告)日：1986-08-26

申请号：US605904

申请日：1984-05-01

申请人： Yuichi Morikawa ,  Hirohiko Sato ,  Eiichi Amada ,  Toshiro Suzuki ,  Hirotoshi Shirasu ,  Hiroshi Kuwahara

发明人： Yuichi Morikawa ,  Hirohiko Sato ,  Eiichi Amada ,  Toshiro Suzuki ,  Hirotoshi Shirasu ,  Hiroshi Kuwahara

IPC分类号： H04B3/03 ,  H04B3/20 ,  H04B3/23 ,  H04B1/58

CPC分类号： H04B3/03 ,  H04B3/23

摘要： In an interface circuit which couples a two-wire line of bidirectional transmission and unidirectional four-wire receiving and transmitting lines; in order to permit the interface circuit to operate in adaptation to the fluctuation of an impedance with the two-wire line side viewed from the four-wire receiving line, the four-wire receiving line is provided with a plurality of filters and a group of switches for selecting the filters, an output of the four-wire transmitting line is compared with outputs obtained by scanning the filters, and the filter providing the minimum output difference in the comparisons is selected and connected.

摘要翻译： 在耦合双向传输双线线路和单向四线接收和发射线路的接口电路中; 为了允许接口电路适应于从四线接收线观察到的双线线路的阻抗的波动，四线接收线路设置有多个滤波器和一组 用于选择滤波器的开关，将四线传输线的输出与通过扫描滤波器获得的输出进行比较，并选择并连接提供比较中最小输出差的滤波器。

公开(公告)号：US4500999A

公开(公告)日：1985-02-19

申请号：US444227

申请日：1982-11-24

申请人： Hiroshi Takatori ,  Toshiro Suzuki

发明人： Hiroshi Takatori ,  Toshiro Suzuki

IPC分类号： H03H15/00 ,  H04B3/06 ,  H04B3/14

CPC分类号： H04B3/145

摘要： A line equalizer including a .sqroot.f equalizer for compensating a .sqroot.f-characteristic of a transmission line, a BT equalizer connected in series with the .sqroot.f equalizer for removing an echo component caused by a bridged tap (namely, BT) on the transmission line, and a circuit for controlling the .sqroot.f equalizer is disclosed. A signal applied to the .sqroot.f equalizer is subjected to over-equalization to make the time domain length of impulse response at the output of the .sqroot.f equalizer small. The equalization state of the output of the .sqroot.f equalizer is judged by signals formed in the BT equalizer, and the gain of the .sqroot.f equalizer is controlled on the basis of the result of judgement. In this manner, the .sqroot.f equalizer is controlled without suffering any interference between a control loop of the .sqroot.f equalizer and a control loop of the BT equalizer.

摘要翻译： 包括用于补偿传输线的2ROOT f特性的2ROOT f均衡器的线均衡器，与2ROOT f均衡器串联连接的BT均衡器，用于消除由传输线上的桥接抽头（即BT）引起的回波分量 并且公开了用于控制2ROOT f均衡器的电路。 施加到2ROOT f均衡器的信号经过过均衡，使得2ROOT f均衡器的输出端的脉冲响应的时域长度较小。 通过在BT均衡器中形成的信号判断2ROOT f均衡器的输出的均衡状态，并根据判断结果控制2ROOT f均衡器的增益。 以这种方式，可以控制2ROOT f均衡器，而不会在2ROOT f均衡器的控制回路和BT均衡器的控制回路之间产生任何干扰。

公开(公告)号：US4459698A

公开(公告)日：1984-07-10

申请号：US358437

申请日：1982-03-15

申请人： Osamu Yumoto ,  Toshiro Suzuki ,  Hiroshi Takatori ,  Yoshitaka Takasaki

发明人： Osamu Yumoto ,  Toshiro Suzuki ,  Hiroshi Takatori ,  Yoshitaka Takasaki

IPC分类号： H03H7/01 ,  H03H19/00 ,  H04B3/06 ,  H04L25/03 ,  H04L25/04

CPC分类号： H04L25/03019

摘要： A small-sized LSI variable equalizer is provided for accurately equalizing waveforms of signals transmitted via transmission lines of different distances. Variable equalizer units capable of stepwise changing the equalizing characteristics thereof are connected in series with each other with the variable equalizer units having variable step widths different from each other. An output signal of the variable equalizer units is compared with a reference signal to convert the comparison output signal to a digital signal which includes an upper order bits and lower order bits, whereby one of the equalizer units which has a wide variable step width is controlled by the upper order bits and the other of the equalizer units which has a narrow variable step width is controlled by the lower order bits.

摘要翻译： 提供小型LSI可变均衡器，用于精确地均衡通过不同距离的传输线传输的信号的波形。 能够逐步改变其均衡特性的可变均衡器单元彼此串联连接，而可变均衡器单元具有彼此不同的可变步长。 将可变均衡器单元的输出信号与参考信号进行比较，以将比较输出信号转换为包括高阶位和低位位的数字信号，由此控制具有宽可变步长的均衡器单元之一 通过较低阶比特和具有窄可变步宽的均衡器单元中的另一个由较低阶比特来控制。

公开(公告)号：US4331894A

公开(公告)日：1982-05-25

申请号：US154574

申请日：1980-05-29

申请人： Roubik Gregorian ,  Toshiro Suzuki

发明人： Roubik Gregorian ,  Toshiro Suzuki

IPC分类号： H03H17/00 ,  H03H19/00 ,  H03H11/00 ,  H03F1/34

CPC分类号： H03H19/004

摘要： An interpolation or smoothing filter circuit for a switched-capacitor system which transforms the sampled-and-held output signals from a switched-capacitor filter into sampled-and-held signals with a doubled sample rate. The circuit comprises an operational amplifier whose noninverting input lead is connected to a switched capacitor network which receives the sampled-and-held input signals at the normal sample rate. The network includes two separate capacitors controlled by switches operable at two alternating clock phases and connected to provide the desired summation and holding of charges. Feedback leads connected between the amplifier output lead and its noninverting input lead and containing additional capacitors cooperate with the input network to produce an output signal that is sampled-and-held at twice the sample rate of the input signal.

摘要翻译： 一种用于开关电容器系统的内插或平滑滤波器电路，其将采样和保持的输出信号从开关电容滤波器转换成采样和保持的信号，并具有两倍的采样率。 该电路包括运算放大器，其同相输入引线连接到开关电容器网络，其以正常采样率接收采样和保持的输入信号。 该网络包括由两个可交替的时钟相位操作的开关控制的两个独立的电容器，并连接以提供期望的加法和保持电荷。 连接在放大器输出引线及其同相输入引线之间的反馈引线和包含附加电容器的输入信号与输入网络配合，以产生采样和保持在输入信号采样速率的两倍的输出信号。

公开(公告)号：US4208641A

公开(公告)日：1980-06-17

申请号：US892420

申请日：1978-03-31

申请人： Toshiro Suzuki

发明人： Toshiro Suzuki

IPC分类号： H03H11/40 ,  H03H11/52 ,  H03H5/04

CPC分类号： H03H11/40 ,  H03H11/525

摘要： A hybrid integrated impedance converter circuit comprising a frequency dependent negative resistance circuit, in which two operational amplifiers are included. Each of the two operational amplifiers has an output terminal and an inverting input terminal, with a negative feedback capacitor being connected between these terminals. The negative feedback capacitor is formed by a stray capacitance which arises between conductors connected to the output and inverting input terminals, which conductors are placed in close proximity to each other.

摘要翻译： 一种混合集成阻抗转换器电路，包括频率依赖负电阻电路，其中包括两个运算放大器。 两个运算放大器中的每一个具有输出端子和反相输入端子，这些端子之间连接有负反馈电容器。 负反馈电容器由连接到输出和反相输入端子的导体之间产生的杂散电容形成，导体彼此靠近放置。