公开(公告)号：US6031389A

公开(公告)日：2000-02-29

申请号：US951618

申请日：1997-10-16

申请人： Bahram Fotouhi ,  Roubik Gregorian

发明人： Bahram Fotouhi ,  Roubik Gregorian

IPC分类号： H03K19/003 ,  H03K17/16

CPC分类号： H03K19/00361

摘要： A slew-rate limited output driver circuit that minimizes switching current while delivering sufficient peak load currents is disclosed. The circuit of the present invention includes fixed pull-up and pull-down transistors that are designed to dissipate minimum switching current while maintaining a predetermined slew rate. Additional pull-up and pull-down transistors are then switched in parallel to the fixed pull-up and pull-down transistors to drive the output all the way to full logic levels, after the output signal has made most of its transition. In a preferred embodiment, each switched transistor is controlled by a comparator that generates its output by comparing the level of the output signal to a predetermined reference voltage.

摘要翻译： 公开了一种在提供足够的峰值负载电流的同时使开关电流最小化的转换速率限制输出驱动器电路。 本发明的电路包括固定的上拉和下拉晶体管，其设计成在保持预定的转换速率的同时消耗最小的开关电流。 然后，在输出信号进行大部分转换之后，附加的上拉和下拉晶体管与固定的上拉和下拉晶体管并联，将输出驱动到完全逻辑电平。 在优选实施例中，每个开关晶体管由比较器控制，该比较器通过将输出信号的电平与预定参考电压进行比较来产生其输出。

公开(公告)号：US4866389A

公开(公告)日：1989-09-12

申请号：US208285

申请日：1988-06-17

申请人： John G. Ryan ,  Roubik Gregorian

发明人： John G. Ryan ,  Roubik Gregorian

IPC分类号： G01R19/00

CPC分类号： G01R19/0084

摘要： A voltage measurement circuit is provided which can be used in a single supply situation, which has a measurement range from rail to rail and which uses a reference voltage which can lie anywhere between the rails but not at the rail to which measurements are to be referenced. The unknown voltage is sampled to a first plate of a capacitor. The second plate of the capacitor is connected to ground. The first plate of the capacitor is then connected to the first input of a comparator, the second input being connected to receive the reference voltage. If the unknown voltage is less than the reference voltage, the second plate of the capacitor is disconnected from ground and then connected to receive the reference voltage. Otherwise it remains connected to ground. The first plate of the capacitor is then connected to a constant current source, causing the voltage at the first comparator input to decrease linearly with time. By measuring the elapsed time between the connection of the first capacitor plate to the constant current source and a change of state of the comparator due to the voltage decrease at its first input, the difference in voltage between the unknown voltage and the reference voltage or ground can be determined based on the linearity of the time-voltage relationship.

摘要翻译： 提供了一种电压测量电路，可以在单个供电情况下使用，其具有从轨到轨的测量范围，并且使用可以位于轨道之间的任何地方但不在测量参考的轨道处的参考电压 。 未知电压被采样到电容器的第一板。 电容器的第二块接地。 然后将电容器的第一板连接到比较器的第一输入端，第二输入端连接以接收参考电压。 如果未知电压小于参考电压，则电容器的第二块与地线断开，然后连接以接收参考电压。 否则，它仍然连接到地面。 然后将电容器的第一板连接到恒流源，使第一比较器输入端的电压随时间线性减小。 通过测量第一电容器板与恒流源的连接之间的经过时间以及由于其第一输入端的电压降低引起的比较器的状态变化，未知电压与参考电压或地之间的电压差 可以基于时间 - 电压关系的线性度来确定。

公开(公告)号：US4179665A

公开(公告)日：1979-12-18

申请号：US940473

申请日：1978-09-08

申请人： Roubik Gregorian

发明人： Roubik Gregorian

IPC分类号： H03H15/00 ,  H03H17/04 ,  H03H19/00 ,  H03F1/36

CPC分类号： H03H19/004 ,  H03H15/00

摘要： A switched capacitor sampled data elliptic filter for data transmission or communication systems is disclosed. The filter section comprises three integrating operational amplifiers connected in series with a negative feedback connection between the output of the second operational amplifier and the input to the first operational amplifier, which is also connected to the input voltage source. Signals via a feed forward connection from the input voltage source and the outputs of the first and second operational amplifiers are summed by the third operational amplifier. Switched capacitors in the feed forward connection, the negative feedback connection, the inputs to all three operational amplifiers and in feedback sections of the first and third operational amplifiers are all connected to a two-phase clock driver operated at a preselected frequency. The circuit arrangement realizes finite transmission zeros in the transfer function which produce a sharp transition from pass band to stop band with a lower order, and the values of all capacitors may be calculated to provide the filter with a loss response within preselected limits.

摘要翻译： 公开了用于数据传输或通信系统的开关电容器采样数据椭圆滤波器。 滤波器部分包括与第二运算放大器的输出端和第一运算放大器的输入端之间的负反馈连接串联的三个积分运算放大器，该输入端也连接到输入电压源。 通过来自输入电压源的前馈连接和第一和第二运算放大器的输出的信号由第三运算放大器相加。 前馈连接中的开关电容，负反馈连接，所有三个运算放大器的输入以及第一和第三运算放大器的反馈部分都连接到以预选频率运行的两相时钟驱动器。 该电路装置实现传递函数中的有限传输零点，其产生从低通滤波器到阻带的尖锐转变，并且可以计算所有电容器的值，以在滤波器的预选极限内提供损耗响应。

公开(公告)号：US20110044216A1

公开(公告)日：2011-02-24

申请号：US12916416

申请日：2010-10-29

申请人： Roubik Gregorian ,  Gaurav Malhotra

发明人： Roubik Gregorian ,  Gaurav Malhotra

IPC分类号： H04B3/20

CPC分类号： H04B3/23

摘要： A method and system are described for canceling an echo signal in analog domain with adaptive filters working in digital domain. In one embodiment a system includes an analog-to-digital converter (ADC) sampling at two different phases to generate a first error signal and a second error signal having different phases. The ADC operates at a frequency significantly lower than the frequency at which the individual filters run. The first adaptive filter unit and a second adaptive filter unit are independently trained with the first and second error signals. respectively. The first and second adaptive filter units generate echo estimate signals used to cancel the echo signal.

摘要翻译： 描述了一种用于在数字域中工作的自适应滤波器在模拟域中消除回波信号的方法和系统。 在一个实施例中，系统包括在两个不同相位处的模数转换器（ADC）采样以产生具有不同相位的第一误差信号和第二误差信号。 ADC的工作频率明显低于单个滤波器运行的频率。 第一自适应滤波器单元和第二自适应滤波器单元被独立地用第一和第二误差信号训练。 分别。 第一和第二自适应滤波器单元产生用于消除回波信号的回波估计信号。

公开(公告)号：US07839758B1

公开(公告)日：2010-11-23

申请号：US12236408

申请日：2008-09-23

申请人： Roubik Gregorian ,  Gaurav Malhotra

发明人： Roubik Gregorian ,  Gaurav Malhotra

IPC分类号： H04J1/12

CPC分类号： H04B3/23

摘要： A method and system are described for canceling an echo signal with an echo canceller in the analog domain. In one embodiment, a system includes an echo canceller that includes an interpolation filter unit, operating in a digital domain, that receives a first digital echo estimate signal from a LMS unit and generates a second digital echo estimate signal without oversampling. A digital-to-analog converter (DAC) receives the second digital echo estimate signal and generates an analog echo estimate signal without oversampling. The echo canceller prevents the DAC from adding a high frequency component to the analog echo estimate signal. A subtractor adds the analog echo estimate signal to an incoming signal having an echo signal. The subtractor generates an analog signal with reduced echo signal in the useful frequency band of the incoming signal.

摘要翻译： 描述了用于在模拟域中用回波消除器消除回波信号的方法和系统。 在一个实施例中，系统包括回波消除器，其包括在数字域中操作的内插滤波器单元，该内插滤波器单元从LMS单元接收第一数字回波估计信号，并产生第二数字回波估计信号而不进行过采样。 数模转换器（DAC）接收第二数字回波估计信号并产生模拟回波估计信号而不进行过采样。 回波消除器防止DAC向模拟回波估计信号添加高频分量。 减法器将模拟回波估计信号添加到具有回波信号的输入信号。 减法器在输入信号的有用频带中产生具有减小的回波信号的模拟信号。

公开(公告)号：US5221890A

公开(公告)日：1993-06-22

申请号：US851924

申请日：1992-03-16

申请人： Jyn-Bang Shyu ,  Roubik Gregorian

发明人： Jyn-Bang Shyu ,  Roubik Gregorian

IPC分类号： G05F1/46 ,  H03M1/06 ,  H03M1/74

CPC分类号： H03M1/0604 ,  G05F1/462 ,  H03M1/745

摘要： An apparatus for generating a substantially constant voltage control signal using either one of a voltage reference source and a current reference source includes a transistor device responsive to a supply voltage and the voltage control signal to produce a controlled current, an operational amplifier device for generating the voltage control signal in response to the voltage reference source, and a switching device for generating the voltage control signal in response to the current reference source. When the switching device is in one state thereof, an output signal of the operational amplifier device is connected through the transistor device in a closed loop back to an input terminal of the operational amplifier device. When the switching device is in another state thereof, the output signal of the operational amplifier device is connected directly in the closed loop back to an input terminal of the operational amplifier device. In particular, the switching device may be a single-pole, single-throw switch realized using either a pass gate device or a bonding wire option Circuit complexity is therefore reduced.

摘要翻译： 用于使用电压参考源和电流参考源中的任一个产生基本上恒定的电压控制信号的装置包括响应于电源电压和电压控制信号以产生受控电流的晶体管器件，用于产生 响应于电压参考源的电压控制信号;以及用于响应于当前参考源产生电压控制信号的开关装置。 当开关器件处于其一个状态时，运算放大器器件的输出信号通过晶体管器件以闭环回路连接到运算放大器器件的输入端。 当开关装置处于其它状态时，运算放大器装置的输出信号直接连接到运算放大器装置的输入端。 特别地，开关器件可以是使用通过栅极器件或接合线选项实现的单极单掷开关。因此，电路复杂度降低。

公开(公告)号：US06798857B2

公开(公告)日：2004-09-28

申请号：US09728295

申请日：2000-12-01

申请人： Roubik Gregorian ,  Shih-Chung Fan

发明人： Roubik Gregorian ,  Shih-Chung Fan

IPC分类号： H04L702

CPC分类号： H03L7/091 ,  H03L7/0814 ,  H04L7/0331 ,  H04L7/0337

摘要： A clock recovery circuit which has a transition detector connected to the incoming data stream. An output of the transition detector is connected to a gate, such as a D flip-flop, which has an input receiving the recovered clock. A zero or one output will be generated depending upon whether the transition is before or after the rising edge of the recovered clock. An accumulator circuit accumulates a count for each transition, providing the results to a comparison circuit. The comparison circuit compares the accumulated count to maximum and minimum thresholds, and provides advance or retard outputs when those thresholds are exceeded. A phase circuit adjusts the phase of the recovered clock by advancing or retarding it after a sufficient number of transitions have been detected either in advance or behind the recovered clock to justify such an adjustment.

摘要翻译： 具有连接到输入数据流的转换检测器的时钟恢复电路。 转换检测器的输出连接到诸如D触发器的门，其具有接收恢复的时钟的输入。 根据转换是否在恢复的时钟的上升沿之前或之后，将产生零或一个输出。 累加器电路为每个转换累加计数，将结果提供给比较电路。 比较电路将累积计数与最大和最小阈值进行比较，并在超过这些阈值时提供提前或延迟输出。 相位电路在已经在恢复的时钟之前或之后检测到足够数量的转换之后通过前进或延迟来调整恢复的时钟的相位，以证明这种调整。

公开(公告)号：US6121837A

公开(公告)日：2000-09-19

申请号：US191450

申请日：1998-11-12

申请人： Roubik Gregorian ,  Saied Rafati

发明人： Roubik Gregorian ,  Saied Rafati

IPC分类号： H03F3/30 ,  H03F3/45

CPC分类号： H03F3/3023 ,  H03F3/45183 ,  H03F2203/45646 ,  H03F2203/45658 ,  H03F2203/45732

摘要： An operational amplifier that exhibits a relatively constant gain over process and temperature variations. The operational amplifier according to the present invention is designed such that its gain does not depend on process sensitive parameters such as mobility of field effect transistors.

摘要翻译： 运算放大器在过程和温度变化上表现出相对恒定的增益。 根据本发明的运算放大器被设计成使得其增益不依赖于诸如场效应晶体管的移动性的过程敏感参数。

公开(公告)号：US5489902A

公开(公告)日：1996-02-06

申请号：US233928

申请日：1994-04-28

申请人： Jyn-Bang Shyu ,  Roubik Gregorian

发明人： Jyn-Bang Shyu ,  Roubik Gregorian

IPC分类号： H03M1/00 ,  H03M1/74 ,  H03M1/66

CPC分类号： H03M1/002 ,  H03M1/742

摘要： Power dissipation is reduced in a video DAC by providing a sleep mode in which DAC current sources are shut off during the blanking period in a manner that allows them to be rapidly turned back on at the end of sleep mode. In particular, a digital to analog converter includes a current source for producing a current, a current steering circuit connected to the current source, the current steering circuit including switches responsive to first and second control signals, respectively, for steering the current into either a load or a current return path, and a control circuit for generating the first and second signals each as a logical combination of a video data signal and a sleep signal. The sleep signal, when it is active, causes both the first and second switches to turn off, which in turn causes the current source to turn off. In a preferred embodiment, the switches are MOSFETS having low gate capacitance. At the end of sleep mode, the current source may be rapidly turned back on by turning on one of the MOSFETS. Performance of the video DAC is therefore not affected, while power dissipation is substantially reduced, facilitating higher-level integration and compliance with the Green PC standard. Reduced power dissipation also allows for use of an inexpensive chip package, reducing manufacturing cost, and increases reliability of the chip.

摘要翻译： 通过提供睡眠模式，在消隐期间切断DAC电流源，使睡眠模式在休眠模式结束时快速转回，这样就可以降低视频DAC的功耗。 特别地，数模转换器包括用于产生电流的电流源，连接到电流源的电流转向电路，电流转向电路包括分别响应于第一和第二控制信号的开关，用于将电流转向到 负载或电流返回路径，以及用于产生每个作为视频数据信号和睡眠信号的逻辑组合的第一和第二信号的控制电路。 睡眠信号当它处于活动状态时，使第一和第二开关都断开，这又导致电流源关闭。 在优选实施例中，开关是具有低栅极电容的MOSFET。 在睡眠模式结束时，可以通过打开其中一个MOSFETS来快速地重新开启电流源。 因此，视频DAC的性能不受影响，而功耗大大降低，便于更高层次的集成和符合绿色PC标准。 降低的功耗也允许使用便宜的芯片封装，降低制造成本，并提高芯片的可靠性。

公开(公告)号：US5258761A

公开(公告)日：1993-11-02

申请号：US851923

申请日：1992-03-16

申请人： Bahram Fotouhi ,  Roubik Gregorian

发明人： Bahram Fotouhi ,  Roubik Gregorian

IPC分类号： H03M1/14 ,  H03M1/76 ,  H03M1/80

CPC分类号： H03M1/145 ,  H03M1/76 ,  H03M1/804

摘要： A circuit technique to achieve 14-bit resolution in a charge-redistribution CMOS analog-to-digital converter. The sign bit plus the six most significant bits are obtained using a 6-bit capacitor array, the next five bits are determined using a resistor array, and finally the last two bits are obtained by use of a second 2-bit capacitor array. The area of the resulting 14-bit A/D converter is not appreciably larger than a corresponding 12-bit A/D converter. The 6-bit capacitor array is realized by connecting unit capacitors of a unit capacitor array. In the second capacitor array, at least one of the capacitors is realized by subdividing the unit capacitor. Since the accuracy of capacitors in the second capacitor array need not be as great as the accuracy of capacitors in the 6-bit capacitor array, subdividing the unit capacitor does not affect the accuracy of the converter.

摘要翻译： 在电荷再分配CMOS模数转换器中实现14位分辨率的电路技术。 符号位加上六个最高有效位是使用6位电容器阵列获得的，接下来的五位是使用电阻阵列来确定的，最后通过使用第二个2位电容器阵列获得最后两位。 所产生的14位A / D转换器的面积不会相当于相应的12位A / D转换器。 6位电容阵列是通过连接单位电容阵列的单位电容来实现的。 在第二电容器阵列中，通过对单位电容器进行细分来实现至少一个电容器。 由于第二电容器阵列中的电容器的精度不需要与6位电容器阵列中的电容器的精度一样大，所以细分单位电容器不会影响转换器的精度。