公开(公告)号：US20120256230A1

公开(公告)日：2012-10-11

申请号：US13081500

申请日：2011-04-07

申请人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L29/7397 ,  H01L29/4236 ,  H01L29/66348

摘要： A power device with trenched gate structure, includes: a substrate having a first face and a second face opposing to the first face, a body region of a first conductivity type disposed in the substrate, a base region of a second conductivity type disposed in the body region, a cathode region of the first conductivity type disposed in the base region, an anode region of the second conductivity type disposed in the substrate at the second face a trench disposed in the substrate and extending from the first face into the body region, and the cathode region encompassing the trench, wherein the trench has a wavelike sidewall, a gate structure disposed in the trench and an accumulation region disposed in the body region and along the wavelike sidewall. The wavelike sidewall can increase the base current of the bipolar transistor and increase the performance of the IGBT.

摘要翻译： 具有沟槽栅极结构的功率器件包括：具有第一面和与第一面相对的第二面的衬底，设置在衬底中的第一导电类型的主体区域，设置在第二导电类型的基极区域 设置在所述基底区域中的所述第一导电类型的阴极区域，所述第二导电类型的阳极区域设置在所述基板的所述第二面处，所述沟槽设置在所述基板中并且从所述第一面延伸到所述主体区域中， 以及包围所述沟槽的阴极区域，其中所述沟槽具有波状侧壁，设置在所述沟槽中的栅极结构以及设置在所述体区中并沿着所述波浪形侧壁的堆积区域。 波形侧壁可以增加双极晶体管的基极电流并增加IGBT的性能。

公开(公告)号：US08278732B1

公开(公告)日：2012-10-02

申请号：US13096995

申请日：2011-04-28

申请人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L23/52

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse element for an integrated circuit is provided, including a conductive region formed in a semiconductor substrate, extending along a first direction; a dielectric layer formed on a portion of the conductive region; a first conductive plug formed on the dielectric layer; a second conductive plug formed on another portion of the conductive region; and a first conductive member formed over the first and second conductive plugs, extending along a second direction perpendicular to the first direction; and a second conductive member formed over the second conductive plug extending along the second direction, wherein the first conductive member intersects with the conductive region, having a first overlapping area therebetween, and the dielectric layer and the conductive region have a second overlapping area therebetween, and a ratio between the first overlapping area and the second overlapping area is about 1.5:1 to 3:1.

摘要翻译： 提供了一种用于集成电路的反熔丝元件，包括形成在半导体衬底中的导电区域，沿着第一方向延伸; 形成在所述导电区域的一部分上的电介质层; 形成在所述电介质层上的第一导电插塞; 形成在所述导电区域的另一部分上的第二导电插塞; 以及第一导电构件，形成在所述第一和第二导电插塞上，沿着垂直于所述第一方向的第二方向延伸; 以及形成在所述第二导电插塞上的第二导电构件，所述第二导电插塞沿着所述第二方向延伸，其中所述第一导电构件与所述导电区域相交，所述导电区域之间具有第一重叠区域，并且所述介电层和所述导电区域之间具有第二重叠区域 并且第一重叠区域和第二重叠区域之间的比率为约1.5：1至3：1。

公开(公告)号：US08975137B2

公开(公告)日：2015-03-10

申请号：US13179581

申请日：2011-07-11

申请人： Wen-Chieh Wang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Wen-Chieh Wang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/461 ,  H01L21/3065 ,  H01L21/308

CPC分类号： H01L21/3065 ,  H01L21/3085

摘要： A process of forming a slit in a substrate is provided. A mask layer is formed on a substrate, wherein the mask layer does not include carbon. An etching process is performed to be substrate by using the mask layer as a mask, so as to form a slit in the substrate. The etching gas includes Cl2, CF4 and CHF3, a molar ratio of CF4 to CHF3 is about 0.5-0.8, and a molar ratio of F to Cl is about 0.4-0.8, for example. Further, the step of performing the etching process simultaneously removes the mask layer.

摘要翻译： 提供了在基板中形成狭缝的工艺。 在基板上形成掩模层，其中掩模层不包括碳。 通过使用掩模层作为掩模，进行蚀刻处理，以便在衬底中形成狭缝。 蚀刻气体包括Cl 2，CF 4和CHF 3，CF 4与CHF 3的摩尔比为约0.5-0.8，F与Cl的摩尔比例如约为0.4-0.8。 此外，进行蚀刻处理的步骤同时去除掩模层。

公开(公告)号：US08772119B2

公开(公告)日：2014-07-08

申请号：US13236656

申请日：2011-09-20

申请人： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/336

CPC分类号： H01L29/66606 ,  H01L21/28044 ,  H01L29/66553 ,  H01L29/78

摘要： A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain.

摘要翻译： 提供晶体管的制造方法。 图案化的牺牲层形成在衬底上，其中图案化牺牲层包括暴露衬底的多个开口。 通过使用图案化牺牲层作为掩模，在衬底上进行掺杂工艺，从而在由开口暴露的衬底中形成掺杂源极区域和掺杂漏极区域。 执行选择性生长工艺以在掺杂源极区域和掺杂漏极区域上分别形成源极和漏极。 去除图案化牺牲层以暴露源极和漏极之间的衬底。 在源极和漏极之间的衬底上形成栅极。

公开(公告)号：US08739806B2

公开(公告)日：2014-06-03

申请号：US13105874

申请日：2011-05-11

申请人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： B08B3/04

CPC分类号： H01L21/67219 ,  B24B37/107 ,  B24B57/02 ,  H01L21/02052 ,  H01L21/67046

摘要： A chemical mechanical polishing (CMP) system includes a wafer polishing unit comprising a waste liquid sink for receiving a used slurry and a waste slurry drain piping for draining the used slurry; and a post-CMP cleaning unit coupled to the wafer polishing unit such that a used base chemical such as tetramethyl ammonium hydroxide (TMAH) produced from the post-CMP cleaning unit flows toward the wafer polishing unit to frequently wash at least the waste slurry drain piping in a real time fashion on a wafer by wafer basis.

摘要翻译： 化学机械抛光（CMP）系统包括晶片抛光单元，其包括用于接收使用过的浆料的废液槽和用于排出所用浆料的废浆排放管道; 以及与CMP晶片抛光单元联接的后CMP清洁单元，使得由CMP后清洁单元生产的诸如四甲基氢氧化铵（TMAH）的使用的基础化学品流向晶片抛光单元，以至少频繁地洗涤废料排水 以晶圆为基础，以实时的方式在晶圆上进行配管。

公开(公告)号：US08662963B2

公开(公告)日：2014-03-04

申请号：US13106822

申请日：2011-05-12

申请人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： B24B55/00

CPC分类号： H01L21/02057 ,  B24B37/34 ,  B24B57/02 ,  H01L21/67046

摘要： A chemical mechanical polishing (CMP) system includes a wafer polishing unit producing a used slurry; a slurry treatment system for receiving and treating the used slurry to thereby produce an extracted basic solution; and a post-CMP cleaning unit utilizing the extracted basic solution to wash a polished wafer surface. The post-CMP cleaning unit includes a plurality of rollers for supporting and rotating a wafer, a brush for scrubbing the wafer, and a spray bar disposed in proximity to the brush for spraying the extracted basic solution onto the polished wafer surface.

摘要翻译： 化学机械抛光（CMP）系统包括生产所用浆料的晶片抛光单元; 用于接收和处理所使用的浆料从而产生提取的碱性溶液的浆料处理系统; 以及利用所提取的碱性溶液洗涤抛光的晶片表面的后CMP清洁单元。 后CMP清洁单元包括用于支撑和旋转晶片的多个辊，用于洗涤晶片的刷子和布置在刷子附近的喷杆，用于将提取的碱性溶液喷射到抛光的晶片表面上。

公开(公告)号：US08592320B2

公开(公告)日：2013-11-26

申请号：US13210172

申请日：2011-08-15

申请人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/302

CPC分类号： H01L29/7854 ,  H01L29/7853

摘要： A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate.

摘要翻译： 提供了一种制造鳍状半导体结构的方法，包括：提供半导体衬底和形成在其上的介电层的半导体衬底; 在所述半导体岛和所述电介质层上形成掩模层; 在所述掩模层中形成开口，使所述半导体岛的上表面和与所述半导体岛相邻的所述电介质层的部分露出; 进行蚀刻处理，同时蚀刻掩模层的一部分，以及由开口暴露的半导体岛和电介质层的部分; 并且去除掩模层和电介质层，在半导体衬底上留下具有弯曲顶表面和各种厚度的蚀刻半导体岛。

公开(公告)号：US08546234B2

公开(公告)日：2013-10-01

申请号：US13154427

申请日：2011-06-06

申请人： Wen-Chieh Wang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Wen-Chieh Wang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/20

CPC分类号： H01L29/66621 ,  H01L21/26506 ,  H01L21/26513 ,  H01L27/10876

摘要： A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion.

摘要翻译： 提供半导体工艺。 在衬底上形成掩模层，并且具有暴露衬底的一部分的第一开口。 使用掩模层作为掩模，在基板上进行干蚀刻处理，以在其中形成第二开口。 第二开口具有底部和从底部向上并向外延伸的侧壁，其中底部由第一开口暴露，并且侧壁被掩模层覆盖。 使用掩模层作为掩模，在底部进行垂直离子注入工艺。 进行转换处理，以在第二开口的侧壁和底部形成转换层，其中侧壁上的转换层的厚度大于底部上的转换层的厚度。

公开(公告)号：US08545289B2

公开(公告)日：2013-10-01

申请号：US13086367

申请日：2011-04-13

申请人： Chien-Mao Liao ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chien-Mao Liao ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： B24B49/00

CPC分类号： H01L21/67259 ,  B24B37/005 ,  B24B37/30 ,  B24B49/08 ,  B24B49/10 ,  B24B49/12 ,  H01L21/68735

摘要： A distance monitoring device is provided. The device is suitable for a chemical mechanical polishing (CMP) apparatus. A polishing head of the CMP apparatus includes a frame and a membrane. The membrane is mounted on the frame, and a plurality of air bags is formed by the membrane and the frame in the polishing head. The distance monitoring device includes a plurality of distance detectors disposed on the frame corresponding to the air bags respectively to set a location of each of the distance detectors on the frame as a reference point, wherein each of the distance detectors is configured to measure a distance between each of the reference points and the membrane.

摘要翻译： 提供了一种距离监测装置。 该设备适用于化学机械抛光（CMP）设备。 CMP设备的抛光头包括框架和膜。 膜安装在框架上，并且多个气囊由抛光头中的膜和框架形成。 距离监视装置包括多个距离检测器，其分别布置在与气囊对应的框架上，以将每个距离检测器的位置设置在框架上作为参考点，其中每个距离检测器被配置成测量距离 在每个参考点和膜之间。

公开(公告)号：US20130102123A1

公开(公告)日：2013-04-25

申请号：US13276960

申请日：2011-10-19

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/02

CPC分类号： H01L27/10867

摘要： A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess.

摘要翻译： 一种掩埋带的制造方法包括：在半导体衬底中形成沟槽电容器结构，其中沟槽电容器结构具有掺杂多晶硅层和由掺杂多晶硅层覆盖的隔离环，以及掺杂多晶硅层的顶表面 低于半导体衬底的顶表面，从而形成第一凹槽; 在半导体衬底上依次形成第一抗蚀剂层，第二抗蚀剂层和第三抗蚀剂层; 顺序地图案化第三抗蚀剂层，第二抗蚀剂层和第一抗蚀剂层，在半导体衬底上形成图案化的三层抗蚀剂层; 部分地去除由图案化的三层抗蚀剂层暴露的部分掺杂多晶硅层以形成第二凹槽; 去除图案化的三层抗蚀剂层; 以及在所述第二凹部中形成绝缘层和所述第一凹部的一部分。