公开(公告)号：US08633091B2

公开(公告)日：2014-01-21

申请号：US13802262

申请日：2013-03-13

Applicant: Xintec Inc.

Inventor： Chia-Lun Tsai ,  Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L21/30 ,  H01L21/301

CPC classification number: H01L21/78 ,  H01L21/76898 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/023 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.

Abstract translation: 芯片封装包括具有焊盘区域，器件区域和位于衬底周围的残留刻划区域的衬底; 设置在所述焊盘区域上的信号和EMI接地焊盘; 分别穿入基板以暴露信号和EMI接地焊盘的第一和第二开口; 位于所述第一和第二开口中的第一和第二导电层，分别电连接所述信号和所述EMI接地焊盘，其中所述第一导电层和所述信号焊盘与所述残留划线区域的外围分离，并且其中 所述第二导电层和/或所述EMI接地垫的一部分延伸到所述残留划线区域的周边; 以及围绕剩余划线区域的周边的第三导电层，以电连接第二导电层和/或EMI接地垫。

公开(公告)号：US20130168784A1

公开(公告)日：2013-07-04

申请号：US13714218

申请日：2012-12-13

Applicant: Xintec Inc.

Inventor： Hung-Jen Lee ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81C1/0023 ,  B81C1/00301

Abstract: A semiconductor package includes: a chip having a first portion and a second portion disposed on the first portion, wherein the second portion has at least a through hole therein for exposing a portion of the first portion, and the first portion and/or the second portion has a MEMS; and an etch stop layer formed between the first portion and the second portion and partially exposed through the through hole of the second portion. The invention allows an electronic element to be received in the through hole so as for the semiconductor package to have integrated functions of the MEMS and the electronic element. Therefore, the need to dispose the electronic element on a circuit board as in the prior art can be eliminated, thereby saving space on the circuit board.

Abstract translation: 半导体封装包括：具有第一部分和设置在第一部分上的第二部分的芯片，其中第二部分至少在其中具有用于暴露第一部分的一部分的通孔，以及第一部分和/或第二部分 部分具有MEMS; 以及形成在所述第一部分和所述第二部分之间并且部分地暴露于所述第二部分的通孔的蚀刻停止层。 本发明允许电子元件被容纳在通孔中，以便半导体封装具有MEMS和电子元件的集成功能。 因此，可以消除如现有技术那样将电子元件配置在电路板上，从而节省了电路板上的空间。