公开(公告)号：US20240363566A1

公开(公告)日：2024-10-31

申请号：US18139896

申请日：2023-04-26

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Wang Gu Lee ,  Ju Hong Shin ,  Ji Hun Lee

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L24/08 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/80 ,  H01L23/49894 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03845 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/80013 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80815 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0504 ,  H01L2924/05442 ,  H01L2924/059

摘要： In one example, an electronic device, comprises a first component comprising a first component inner side and a first component backside, a first component inner terminal, a first component dielectric at the first component inner side, and a first component interconnect coupled with the first component inner terminal. The electronic device comprises a second component over the first component and comprising a second component inner side facing the first component inner side, and a second component backside, a second component inner terminal, a second component dielectric at the second component inner side, and a second component interconnect coupled with the second component inner terminal. The first component dielectric and the second component dielectric comprise an inorganic material, the first component dielectric is coupled with the second component dielectric, and the first component interconnect is coupled with the second component interconnect. Other examples and related methods are also disclosed herein.

公开(公告)号：US20240363564A1

公开(公告)日：2024-10-31

申请号：US18309678

申请日：2023-04-28

申请人： Tokyo Electron Limited

发明人： Soo Doo CHAE ,  Matthew BARON ,  Adam GILDEA

IPC分类号： H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC分类号： H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/06505 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/1431 ,  H01L2924/1434

摘要： At least one aspect of the present disclosure is directed to a semiconductor device. The semiconductor device includes a first substrate including a first area and a second area; a second substrate including a third area and a fourth area; a first bonding layer comprising a first dielectric material that bonds the first area to the third area; and a second bonding layer comprising a second dielectric material that bonds the second area to the fourth area. The first dielectric material is different from the second dielectric material.

公开(公告)号：US20240347524A1

公开(公告)日：2024-10-17

申请号：US18403022

申请日：2024-01-03

申请人： Samsung Electronics Co., Ltd.

发明人： Joonho Jun ,  Kyomin Sohn ,  Duksung Kim ,  Byoungkon Jo ,  Jangseok Choi

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H10B80/00

CPC分类号： H01L25/18 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L25/50 ,  H10B80/00 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/80357 ,  H01L2224/94 ,  H01L2924/1436

摘要： A semiconductor package according to an example embodiment of the present disclosure includes: a package substrate; and first to third memory dies disposed on the package substrate and sequentially stacked in a first direction, perpendicular to an upper surface of the package substrate, and the first memory die and the second memory die are attached to each other without a bump, and the second memory die and the third memory die are attached to each other by a plurality of bumps.

公开(公告)号：US20240347487A1

公开(公告)日：2024-10-17

申请号：US18368640

申请日：2023-09-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaeean Lee ,  Dahee Kim ,  Taehoon Lee ,  Gyujin Choi

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L24/05 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/06 ,  H01L24/08 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/03462 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0601 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2924/1815

摘要： An upper redistribution wiring layer of a semiconductor package includes a protective layer provided on at least one upper insulating layer and having an opening that exposes at least a portion of an uppermost redistribution wiring among second redistribution wirings, and a bonding pad provided on the uppermost redistribution wiring through the opening. The bonding pad includes a first plating pattern formed on the uppermost redistribution wiring, the first plating pattern including a via pattern provided in the opening and a pad pattern formed on the via pattern to be exposed from the opening, a second plating pattern on the second plating pattern, and a third plating pattern on the second plating pattern.

公开(公告)号：US20240339411A1

公开(公告)日：2024-10-10

申请号：US18395839

申请日：2023-12-26

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： CHENGTAR WU ,  JONGKOOK KIM ,  SEUNGYEON RHEE ,  CHOONGBIN YIM

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

CPC分类号： H01L23/5385 ,  H01L21/486 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： A semiconductor package includes a substrate, a first three-dimensional integrated circuit structure on the substrate, and a second three-dimensional integrated circuit structure on the substrate, where the first three-dimensional integrated circuit structure may include a first interposer including a first semiconductor die, and a second semiconductor die on the first interposer, where the second three-dimensional integrated circuit structure may include a second interposer including a third semiconductor die, and a fourth semiconductor die on the second interposer, where the substrate may include an electrical routing configured to relay a signal from the second semiconductor die and a signal from the fourth semiconductor die.

公开(公告)号：US20240332258A1

公开(公告)日：2024-10-03

申请号：US18494557

申请日：2023-10-25

申请人： SK hynix Inc.

发明人： Da Il RIM

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/528

CPC分类号： H01L25/0657 ,  H01L23/5283 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/05093 ,  H01L2224/05647 ,  H01L2224/80895 ,  H01L2225/06544 ,  H01L2924/351

摘要： A semiconductor device may include: a lower semiconductor structure including a lower semiconductor substrate including a first region and a second region, a lower circuit structure disposed in the first region over the lower semiconductor substrate, a lower bonding pad disposed over the lower circuit structure and connected thereto, and a dummy conductive pattern disposed in the second region over the lower semiconductor substrate; an upper semiconductor structure including an upper semiconductor substrate disposed over the lower semiconductor structure and including the first region and the second region, an upper circuit structure disposed in the first region under the upper semiconductor substrate, and an upper bonding pad disposed under the upper circuit structure and connected thereto while being bonded to the lower bonding pad; a through electrode; and a dummy through electrode passing through the upper semiconductor structure and connected to the dummy conductive pattern.

公开(公告)号：US20240332227A1

公开(公告)日：2024-10-03

申请号：US18194544

申请日：2023-03-31

申请人： ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC

发明人： Cyprian Emeka Uzoh ,  Oliver Zhao

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/03614 ,  H01L2224/0382 ,  H01L2224/03826 ,  H01L2224/03827 ,  H01L2224/03845 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2924/01014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0543

摘要： A semiconductor element having an interconnect bonding layer with a contact pad and a plasma damage-free low-k dielectric material is disclosed. The contact pad connects an underlying conductive feature through an intervening via. A thin dielectric layer is disposed on and covering the entire sidewalls of the contact pad, the intervening via and the underlying conductive feature, and making an approximately right angle turn to extend along an interface between the low-k dielectric material and a first dielectric layer that at least partially bury the underlying contact feature.

公开(公告)号：US20240332033A1

公开(公告)日：2024-10-03

申请号：US18614936

申请日：2024-03-25

申请人： STMicroelectronics International N.V.

发明人： Michele DERAI ,  Guendalina CATALANO

IPC分类号： H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L21/561 ,  H01L21/78 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L24/04 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/13021 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16227 ,  H01L2224/94

摘要： A “package-less” integrated circuit semiconductor device is produced by laminating first and second insulating films on opposed first and second surfaces of a semiconductor wafer having semiconductor dice integrated therein. Electrically conductive formations towards die pads of the semiconductor dice are provided in vias to the semiconductor wafer opened through the first insulating film laminated on the first surface of the semiconductor wafer. The semiconductor wafer provided with these electrically conductive formations is singulated at separation lines between neighboring semiconductor dice to produce individual semiconductor devices. Each device has: opposed first and second device surfaces having protective portions of the first and second insulating films laminated thereon, and side surfaces extending between the opposed first and second device surfaces, these side surfaces being left uncovered by the first and second insulating films.

公开(公告)号：US20240321927A1

公开(公告)日：2024-09-26

申请号：US18680445

申请日：2024-05-31

申请人： SONY GROUP CORPORATION

发明人： Satoru WAKIYAMA ,  Yukio TAGAWA

IPC分类号： H01L27/146 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC分类号： H01L27/14634 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/16 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/1469 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05647 ,  H01L2224/16146 ,  H01L2224/73204

摘要： There is provided an imaging device including: a first semiconductor substrate having a first region that includes a photoelectric conversion section and a via portion, a second region adjacent to the first region, a connection portion disposed at the second region, and a second semiconductor substrate, wherein the connection portion electrically couples the first semiconductor substrate to the second semiconductor substrate in a stacked configuration, and wherein a width of the connection portion is greater than a width of the via portion.

公开(公告)号：US20240321794A1

公开(公告)日：2024-09-26

申请号：US18679806

申请日：2024-05-31

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jeonggi Jin ,  Gyuho Kang ,  Unbyoung Kang ,  Heewon Kim ,  Jumyong Park ,  Hyunsu Hwang

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L24/08 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/02251 ,  H01L2224/05009 ,  H01L2224/05555 ,  H01L2224/05647 ,  H01L2224/08146

摘要： A semiconductor chip includes: a semiconductor substrate; a pad insulating layer on the semiconductor substrate; a through electrode which penetrates the semiconductor substrate and the pad insulating layer and includes a conductive plug and a conductive barrier layer surrounding a sidewall of the conductive plug; and a bonding pad which surrounds a sidewall of the through electrode and is spaced apart from the conductive plug with the conductive barrier layer disposed therebetween.