公开(公告)号：US09069564B1

公开(公告)日：2015-06-30

申请号：US13396007

申请日：2012-02-14

Applicant: Abbas Rashid ,  David T. Hass

Inventor： Abbas Rashid ,  David T. Hass

IPC: G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3802

Abstract: A method and system are provided for performing efficient and effective scheduling in a multi-threaded system. Dynamic control of scheduling is provided, in which priority weights can be assigned for some or all of the threads in the multi-threaded system. The priority weights are employed to control prioritization of threads and thread instructions by a scheduler. An instruction count for each thread is used in combination with the priority weights to determine the prioritization order in which instructions are fetched and assigned to execution units for processing.

Abstract translation: 提供了一种用于在多线程系统中执行有效和有效的调度的方法和系统。 提供了调度的动态控制，其中可以为多线程系统中的一些或所有线程分配优先级权重。 采用优先级权重来控制调度器对线程和线程指令的优先级。 每个线程的指令计数与优先权重组合使用，以确定指令被取出并分配给执行单元进行处理的优先次序顺序。

公开(公告)号：US08990422B1

公开(公告)日：2015-03-24

申请号：US13165768

申请日：2011-06-21

Applicant: Ozair Usmani ,  Kaushik Kuila

Inventor： Ozair Usmani ,  Kaushik Kuila

IPC: G06F15/16 ,  H04L29/06

CPC classification number: H04L69/166 ,  H04L29/06136 ,  H04L49/9042 ,  H04L69/321

Abstract: Systems, apparatusses, and methods are disclosed for transmission control protocol (TCP) segmentation offload (TSO). A hardware TSO engine is capable of handling segmentation of data packets and consequent header field mutation of hundreds of flows simultaneously. The TSO engine generates data pointers in order to “cut up” the payload data of a data packet, thereby creating multiple TCP segments. Once the data of the data packet has been fetched, the TSO engine “packs” the potentially-scattered chunks of data into TCP segments, and recalculates each TCP segment's internet protocol (IP) length, IP identification (ID), IP checksum, TCP sequence number, and TCP checksum, as well as modifies the TCP flags. The TSO engine is able to rapidly switch contexts, and share the control logic amongst all flows.

Abstract translation: 公开了用于传输控制协议（TCP）分段卸载（TSO）的系统，设备和方法。 硬件TSO引擎能够同时处理数据包的分段和数百个流的后续头域突变。 TSO引擎生成数据指针，以便“切断”数据包的有效载荷数据，从而创建多个TCP段。 一旦获取了数据包的数据，TSO引擎将潜在的分散的数据块“打包”成TCP段，并重新计算每个TCP段的Internet协议（IP）长度，IP标识（ID），IP校验和，TCP 序列号和TCP校验和，以及修改TCP标志。 TSO引擎能够快速切换上下文，并在所有流中共享控制逻辑。

公开(公告)号：US08943236B1

公开(公告)日：2015-01-27

申请号：US13166749

申请日：2011-06-22

Applicant: Ozair Usmani

Inventor： Ozair Usmani

IPC: G06F3/00 ,  G06F13/00

CPC classification number: H04L12/6418 ,  G06F13/36 ,  G06F13/385 ,  G06F2213/3808

Abstract: The disclosed packet scheduler implements the deficit round robin (DRR) approximation of weighted fair queuing (WFQ), and is capable of achieving complete fairness across several hundred source flows, for example, each of which can be mapped to one of several destination ports. In addition to achieving fairness, the packet scheduler allows the user to map one or more optional strict-priority flows to each port. The packet scheduler keeps these strict-priority flows “outside” of the group of flows for which fairness is enforced. Each destination port can be optionally configured to chop its data packets into sub-packet pieces. The packet scheduler works in two mutually orthogonal dimensions: (1.) it selects destination ports based on a round-robin scheme, or using another method, such as guaranteed rate port scheduling (GRPS), and (2.) it implements optional strict-priority scheduling, and DRR scheduling.

Abstract translation: 所公开的分组调度器实现加权公平排队（WFQ）的赤字循环（DRR）近似，并且能够实现跨几百个源流的完全公平，例如，每个源流可以映射到几个目的地端口之一。 除了实现公平性之外，分组调度器允许用户将一个或多个可选的严格优先级流映射到每个端口。 分组调度器将这些严格优先级流程保持在执行公平的流程组之外。 每个目标端口可以被选择性地配置成将其数据分组划分成子分组。 分组调度工作在两个相互正交的维度上：（1）基于循环方案选择目标端口，或使用其他方法，如保证速率端口调度（GRPS）和（2.）实现可选严格 优先级调度和DRR调度。

公开(公告)号：US08935270B1

公开(公告)日：2015-01-13

申请号：US12779894

申请日：2010-05-13

Applicant: Cristian Estan ,  Greg Watson

Inventor： Cristian Estan ,  Greg Watson

IPC: G06F7/00 ,  G06F17/30

CPC classification number: G06F7/02 ,  G06F2207/025

Abstract: A content search system for determining whether an input string matches one or more of a number of patterns embodied by a deterministic finite automaton (DFA) includes a plurality of DFA engines that simultaneously compare sequential overlapping segments of the input string. The overlap region shared by adjacent pairs of input string segments is of a predetermined size. Initially, the first DFA engine is designated as the master engine, and the remaining DFA engines are designated as slave engines whose state results are speculative. Resolution logic compares the state results of the master engine with the state results of the adjacent slave engine to selectively validate the state results of the successor engine, which upon validation becomes the new master engine.

Abstract translation: 用于确定输入字符串匹配由确定性有限自动机（DFA）体现的多个模式中的一个或多个的内容搜索系统包括同时比较输入字符串的顺序重叠片段的多个DFA引擎。 相邻输入串段共享的重叠区域具有预定的大小。 最初，第一个DFA引擎被指定为主引擎，其余的DFA引擎被指定为从属引擎，其状态结果是推测性的。 分辨率逻辑将主引擎的状态结果与相邻从属引擎的状态结果进行比较，以选择性地验证后继引擎的状态结果，后者在验证成为新的主引擎时。

公开(公告)号：US08836306B2

公开(公告)日：2014-09-16

申请号：US13618652

申请日：2012-09-14

Applicant: Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

Inventor： Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

IPC: H02M3/157 ,  H02M3/158

CPC classification number: H02M3/1584 ,  H02M2003/1586 ,  Y10T307/582

Abstract: An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

Abstract translation: 用于向负载递送电力的集成电路装置包括控制器电路，级联电路和电力输送电路。 控制器电路产生多个控制信号。 级联电路从控制器电路接收控制信号，并将控制信号依次输出到级联总线上。 功率传递电路响应于控制信号之一，接收来自控制器电路的控制信号并将一定量的电流传送到负载。

公开(公告)号：US08829984B2

公开(公告)日：2014-09-09

申请号：US13555783

申请日：2012-07-23

Applicant: Roy G. Batruni

Inventor： Roy G. Batruni

IPC: H03B1/00

CPC classification number: H04L9/0668 ,  H04K1/00 ,  H04L27/00

Abstract: A system and method are disclosed for securely transmitting and receiving a signal. A nonlinear keying modulator is used in the transmitter to encrypt the signal using a nonlinear keying modulation technique. A nonlinear keying demodulator is used in the receiver to decrypt the signal.

Abstract translation: 公开了用于安全地发送和接收信号的系统和方法。 发射机使用非线性密钥调制器，使用非线性密钥调制技术对信号进行加密。 在接收机中使用非线性键控解调器对信号进行解密。

公开(公告)号：US08754681B2

公开(公告)日：2014-06-17

申请号：US13163605

申请日：2011-06-17

Applicant: Julianne J. Zhu ,  David T. Hass

Inventor： Julianne J. Zhu ,  David T. Hass

IPC: H03L7/06

CPC classification number: H03L7/00

Abstract: An improved approach is described for implementing a clock management system. A multi-part phase locked loop circuit is provided to handle the different clock needs of the circuit, where each of the phase locked loops within the multi-part phase locked loop circuit may feed a clock output to one or more divider circuits. The divider circuits may be dedicated to specific components. For example, a SoC PLL may generate a clock output to a SoC divider that is dedicated to providing a clock to content address memory (CAM) components. This approach allows the clock management system to efficiently generate clock signals with variable levels of frequencies, even for complicated circuits having many different functional portions and components.

Abstract translation: 描述了一种用于实现时钟管理系统的改进方法。 提供多部分锁相环电路以处理电路的不同时钟需要，其中多部分锁相环电路内的每个锁相环可以将时钟输出馈送到一个或多个除法器电路。 分频器电路可以专用于特定部件。 例如，SoC PLL可以产生时钟输出到专用于为内容地址存储器（CAM）组件提供时钟的SoC分频器。 这种方法允许时钟管理系统有效地生成具有可变电平频率的时钟信号，即使对于具有许多不同功能部分和组件的复杂电路也是如此。

公开(公告)号：US20140146967A1

公开(公告)日：2014-05-29

申请号：US13725829

申请日：2012-12-21

Applicant: NetLogic Microsystems, Inc.

Inventor： Roy G. BATRUNI

IPC: H04L9/06

CPC classification number: H04L9/0668 ,  H04K1/00 ,  H04L27/00

Abstract: A system and method are disclosed for securely transmitting and receiving a signal. A nonlinear keying modulator is used in the transmitter to encrypt the signal using a nonlinear keying modulation technique. A nonlinear keying demodulator is used in the receiver to decrypt the signal.

Abstract translation: 公开了用于安全地发送和接收信号的系统和方法。 发射机使用非线性密钥调制器，使用非线性密钥调制技术对信号进行加密。 在接收机中使用非线性键控解调器对信号进行解密。

公开(公告)号：US08724657B2

公开(公告)日：2014-05-13

申请号：US13205420

申请日：2011-08-08

Applicant: Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

Inventor： Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

IPC: H04J3/24 ,  H04L12/56

CPC classification number: H04L49/901 ,  H04L49/9021 ,  H04L49/9042 ,  H04L69/02 ,  H04L69/22 ,  H04L69/26

Abstract: A method and system of packet assembly is provided. The method includes providing a first packet descriptor. The first packet descriptor is a pointer-to-pointer (P2P) descriptor that includes pointer information. The method further includes retrieving a first pointer referenced by the pointer information of the first packet descriptor; providing the first pointer to a DMA engine; and using the DMA engine to retrieve packet data referenced by the first pointer.

Abstract translation: 提供了一种分组组装的方法和系统。 该方法包括提供第一分组描述符。 第一个分组描述符是包括指针信息的指针指针（P2P）描述符。 该方法还包括：检索由第一分组描述符的指针信息引用的第一指针; 提供第一个指向DMA引擎的指针; 并使用DMA引擎来检索由第一个指针引用的数据包数据。

公开(公告)号：US08683177B2

公开(公告)日：2014-03-25

申请号：US13596495

申请日：2012-08-28

Applicant: Scott Smith

Inventor： Scott Smith

IPC: G06F12/00

CPC classification number: G11C15/00

Abstract: A content addressable memory (CAM) (100) can include a CAM memory array (102) having both a data field (102-0) and a mask field (102-1). A multiplexer (MUX) (108) can selectively load data from either a register (104) or an external data input (106) to one or both fields (102-0 and 102-1) of CAM memory array (102).

Abstract translation: 内容可寻址存储器（CAM）（100）可以包括具有数据字段（102-0）和掩码字段（102-1）两者的CAM存储器阵列（102）。 复用器（MUX）（108）可以选择性地将数据从寄存器（104）或外部数据输入（106）加载到CAM存储器阵列（102）的一个或两个场（102-0和102-1）。