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公开(公告)号：US20230068481A1
公开(公告)日：2023-03-02
申请号：US17461734
申请日：2021-08-30
发明人： FU-CHIANG KUO
摘要： A semiconductor trench capacitor structure is provided. The semiconductor trench capacitor comprises a semiconductor substrate; a trench capacitor overlying the semiconductor substrate, wherein the trench capacitor comprises a plurality of trench electrodes and a plurality of capacitor dielectric layers that are alternatingly stacked over the semiconductor substrate and defines a plurality of trench segments and a plurality of pillar segments, wherein the trench electrodes and the capacitor dielectric layers are recessed into the semiconductor substrate at the trench segments, and wherein the trench segments are separated from each other by the pillar segments; and a protection dielectric layer disposed between the semiconductor substrate and the trench capacitor, wherein the protection dielectric layer has a thickness greater than thicknesses of the trench electrodes.
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公开(公告)号：US20230068458A1
公开(公告)日：2023-03-02
申请号：US17459449
申请日：2021-08-27
发明人： Bo-Wen Hsieh , Pei Ying Lai
IPC分类号： H01L29/40 , H01L29/78 , H01L29/423 , H01L29/49
摘要： A gate dielectric structure is formed over a channel structure. One or more work function (WF) metal layers of a metal gate are formed over the gate dielectric structure. The one or more WF metal layers are treated with a fluorine-containing material. One or more processes are performed to cause fluorine from the fluorine-containing material to diffuse at least partially into the gate dielectric structure.
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公开(公告)号：US20230068280A1
公开(公告)日：2023-03-02
申请号：US17463203
申请日：2021-08-31
发明人： Cheng-Yu LIN , Jung-Chan YANG , Hui-Zhong ZHUANG , Sheng-Hsiung CHEN , Kuo-Nan YANG , Chih-Liang CHEN , Lee-Chung LU
IPC分类号： H01L23/528 , H01L23/50 , H01L27/118
摘要： An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.
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公开(公告)号：US20230068279A1
公开(公告)日：2023-03-02
申请号：US17461536
申请日：2021-08-30
发明人： Shih-Yao Lin , Hsiao Wen Lee , Ming-Ching Chang
IPC分类号： H01L29/423 , H01L29/786 , H01L29/06 , H01L29/66 , H01L21/8234
摘要： A semiconductor device includes an active gate structure extending along a first lateral direction. The semiconductor device includes an inactive gate structure also extending along the first lateral direction. The semiconductor device includes a first epitaxial structure disposed between the active gate structure and the inactive gate structure along a second lateral direction perpendicular to the first lateral direction. The active gate structure wraps around each of a plurality of channel layers that extend along the second direction, and the inactive gate structure straddles a semiconductor cladding layer that continuously extends along a first sidewall of the first epitaxial structure and across the plurality of channel layers.
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85.发明申请公开(公告)号：US20230067988A1
公开(公告)日：2023-03-02
申请号：US17460620
申请日：2021-08-30
发明人： Shih-Hao Lin , Chih-Chuan Yang , Hsin-Wen Su , Jing-Yi Lin , Shang-Rong Li , Chong-De Lien
IPC分类号： H01L29/66 , H01L29/423 , H01L29/06 , H01L21/762
摘要： A semiconductor structure includes a stack of semiconductor layers disposed over a protruding portion of a substrate, isolation features disposed over the substrate, wherein a top surface of the protruding portion of the substrate is separated from a bottom surface of the isolation features by a first distance, a metal gate stack interleaved with the stack of semiconductor layers, where a bottom portion of the metal gate stack is disposed on sidewalls of the protruding portion of the substrate and where thickness of the bottom portion of the metal gate stack is defined by a second distance that is less than the first distance, and epitaxial source/drain features disposed adjacent to the metal gate stack.
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公开(公告)号：US20230067952A1
公开(公告)日：2023-03-02
申请号：US17463022
申请日：2021-08-31
发明人： Chih-Yu LAI , Chih-Liang CHEN , Ching-Wei TSAI , Shang-Wen CHANG , Li-Chun TIEN
IPC分类号： H01L27/12
摘要： A semiconductor device includes a base isolation layer, a first transistor with a first source electrode at a first side of the base isolation layer. A bridge pillar extends through the base isolation layer, and a metal electrode electrically connects the bridge pillar to the first source electrode. The metal electrode and the first source electrode are at the same side of the base isolation layer. A second metal electrode at an opposite side of the base isolation layer electrically connects to the bridge pillar and to a conductive line at the second side of the base isolation layer.
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公开(公告)号：US20230067752A1
公开(公告)日：2023-03-02
申请号：US17460208
申请日：2021-08-28
发明人： Ya-Yi Tsai , Yi-Chun Chen , Wei-Han Chen , Wei-Ting Guo , Shu-Yuan Ku
IPC分类号： H01L29/66 , H01L27/088 , H01L29/78 , H01L29/06 , H01L21/8234
摘要： A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.
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公开(公告)号：US20230067734A1
公开(公告)日：2023-03-02
申请号：US17462974
申请日：2021-08-31
IPC分类号： H01L27/02 , H01L23/528 , G06F30/392 , H01L27/118 , H01L23/522 , H01L21/768
摘要： An integrated circuit (IC) device includes a circuit region, a lower metal layer over the circuit region, and an upper metal layer over the lower metal layer. The lower metal layer includes a plurality of lower conductive patterns elongated along a first axis. The upper metal layer includes a plurality of upper conductive patterns elongated along a second axis transverse to the first axis. The plurality of upper conductive patterns includes at least one input or output configured to electrically couple the circuit region to external circuitry outside the circuit region. The upper metal layer further includes a first lateral upper conductive pattern contiguous with and projecting, along the first axis, from a first upper conductive pattern among the plurality of upper conductive patterns. The first lateral upper conductive pattern is over and electrically coupled to a first lower conductive pattern among the plurality of lower conductive patterns.
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公开(公告)号：US20230067696A1
公开(公告)日：2023-03-02
申请号：US17461779
申请日：2021-08-30
发明人： Yu-Lien Huang , Yi-Shan Chen , Kuan-Da Huang , Han-Yu Lin , Li-Te Lin , Ming-Huan Tsai
IPC分类号： H01L29/78 , H01L29/417 , H01L29/40
摘要： A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.
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90.发明申请公开(公告)号：US20230067690A1
公开(公告)日：2023-03-02
申请号：US17460668
申请日：2021-08-30
发明人： Shu-Shen YEH , Chin-Hua WANG , Po-Chen LAI , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L23/00 , H01L23/053 , H01L23/16 , H01L21/52
摘要： A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, a semiconductor device, a ring structure, a lid structure, and an adhesive member. The semiconductor device is disposed over the substrate. The ring structure is disposed over the substrate and surrounds the semiconductor device. The lid structure is disposed over the ring structure and extends across the semiconductor device. The adhesive member is disposed in a gap between the ring structure and the semiconductor device and attached to the lid structure and the substrate.
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