利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

23 条记录 (耗时 0.025 秒)

    POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS
    5.
    发明申请
    POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS 有权

    公开(公告)号：US20230036522A1

    公开(公告)日：2023-02-02

    申请号：US17390177

    申请日：2021-07-30

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chih-Liang CHEN ,  Guo-Huei WU ,  Ching-Wei TSAI ,  Shang-Wen CHANG ,  Li-Chun TIEN

    IPC分类号： H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

    摘要： An integrated circuit device includes a first-type active-region semiconductor structure, a first gate-conductor, a second-type active-region semiconductor structure that is stacked with the first-type active-region semiconductor structure, and a second gate-conductor. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device also includes a front-side power rail and a front-side signal line in the front-side conductive layer and includes a back-side power rail and a back-side signal line in the back-side conductive layer. The integrated circuit device also includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail. The integrated circuit device further includes a drain conductive segment connected to either the front-side signal line or the back-side signal line.

    SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20220310454A1

    公开(公告)日：2022-09-29

    申请号：US17833005

    申请日：2022-06-06

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Shang-Wen CHANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

    IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/768

    摘要： A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.

    METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING SEGMENTED INTERCONNECT
    7.
    发明公开
    METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING SEGMENTED INTERCONNECT 审中-公开

    公开(公告)号：US20240347546A1

    公开(公告)日：2024-10-17

    申请号：US18755041

    申请日：2024-06-26

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chih-Yu LAI ,  Chih-Liang CHEN ,  Ching-Wei TSAI ,  Shang-Wen CHANG ,  Li-Chun TIEN

    IPC分类号： H01L27/12 ,  H01L21/768 ,  H01L23/48

    CPC分类号： H01L27/124 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/1259

    摘要： A method of making a semiconductor device includes manufacturing a first bridge pillar; manufacturing a first transistor channel bar and first transistor source/drain electrode, the first transistor S/D electrode electrically connecting to the first bridge pillar; manufacturing a second transistor channel bar and second transistor S/D electrode; manufacturing a first metal electrode, the first bridge pillar connecting the first transistor S/D electrode and first metal electrode; manufacturing a first via connected to the first metal electrode; and manufacturing a first conductive line connected to the first via. The first transistor S/D electrode and the second transistor S/D electrode are spaced apart by a first height, the first metal electrode is separate from the second transistor S/D electrode, the first bridge pillar is separate from the second transistor S/D electrode, and the first bridge pillar has a height in the first direction substantially equal to the first height.