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公开(公告)号：US20220406716A1
公开(公告)日：2022-12-22
申请号：US17351711
申请日：2021-06-18
发明人： Wan-Yu LO , Chung-Hsing WANG , Chin-Shen LIN , Kuo-Nan YANG , Meng-Xiang LEE , Hao-Tien KAN , Jhih-Hong YE
IPC分类号： H01L23/528 , H01L23/522
摘要： Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
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公开(公告)号：US20220309224A1
公开(公告)日：2022-09-29
申请号：US17840887
申请日：2022-06-15
发明人： Chin-Shen LIN , Ming-Hsien LIN , Kuo-Nan YANG , Chung-Hsing WANG
IPC分类号： G06F30/398 , G06F30/394
摘要： Failure-in-time (FIT) evaluation methods for an IC are provided. Data representing a layout of the IC is accessed, and the layout includes a metal line and a plurality of vertical interconnect accesses (VIAs). The metal line is divided into a first sub-line with a first line width and a second sub-line with a second line width. A plurality of nodes are picked along the first and second sub-lines of the metal line. The metal line is divided into a plurality of metal segments based on the nodes. FIT value is determined for each of the metal segments to verify the layout and fabricate the IC. The first line width is greater than the second line width.
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公开(公告)号：US20220075922A1
公开(公告)日：2022-03-10
申请号：US17527967
申请日：2021-11-16
发明人： Chin-Shen LIN , Hiranmay BISWAS , Kuo-Nan YANG , Chung-Hsing WANG
IPC分类号： G06F30/392
摘要： A system includes a processor configured to determine a power parameter associated with a cell in an integrated circuit (IC) layout diagram. In response to the determined power parameter exceeding a design criterion, the processor is configured to perform a modification of the IC layout diagram, the modification including at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell. The power parameter includes at least one of a power density of a tile containing the cell, a voltage drop of the tile containing the cell, or a voltage drop of the cell.
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4.发明申请公开(公告)号：US20200004915A1
公开(公告)日：2020-01-02
申请号：US16405883
申请日：2019-05-07
发明人： Ritesh KUMAR , Chung-Hsing WANG , Kuo-Nan YANG , Hiranmay BISWAS , Shu-Yi YING
IPC分类号： G06F17/50
摘要： A method (of revising an initial layout diagram of a wire routing arrangement) includes: identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction; the routed patterns being functional in a representation of a circuit; the dummy patterns being non-functional in the representation of the circuit; and revising to form a revised layout diagram, the revising including adding first and second jumper patterns, into a second conductance layer, which extend in a second direction substantially perpendicular to the first direction, and adding via patterns, into an interconnection layer between the first and second conductance layers, which represent (A) connections between the first jumper pattern and first ends of the corresponding routed and dummy patterns, and (B) connections between the second jumper pattern and second ends of the corresponding routed and dummy patterns.
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公开(公告)号：US20230124119A1
公开(公告)日：2023-04-20
申请号：US18066154
申请日：2022-12-14
IPC分类号： H01L27/02 , G06F1/3287
摘要： An integrated circuit includes a gated circuit configured to operate on a first or second voltage, a header circuit, a first power rail and a second power rail on a back-side of a wafer, a third power rail on the back-side of the wafer, and a fourth power rail on a front-side of the wafer. The first and second power rail extend in a first direction, and are separated from each other in a second direction. The third power rail is between the first and second power rail in the second direction. The third power rail is configured to supply the second voltage to the gated circuit. The fourth power rail includes a first set of conductors extending in the second direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit, and is separated from each other in the first direction.
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公开(公告)号：US20220093513A1
公开(公告)日：2022-03-24
申请号：US17544937
申请日：2021-12-08
发明人： Hiranmay BISWAS , Chi-Yeh YU , Kuo-Nan YANG , Chung-Hsing WANG , Stefan RUSU , Chin-Shen LIN
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522
摘要： A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.
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公开(公告)号：US20200074042A1
公开(公告)日：2020-03-05
申请号：US16547065
申请日：2019-08-21
发明人： Hiranmay BISWAS , Chung-Hsing WANG , Kuo-Nan YANG , Jia Han LIN
摘要： A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: populating a row which extends in a first direction with a group of cells, each cell representing a circuit, and first and second side boundaries of each cell being substantially parallel and extending in a second direction which is substantially perpendicular to the first direction; locating, relative to the first direction, cells so that neighboring ones of the cells are substantially abutting; and reducing an aggregate leakage tendency of the group by performing at least one of the following, (A) changing an orientation of at least one of the cells, or (B) changing locations correspondingly of at least two of the cells.
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公开(公告)号：US20150278427A1
公开(公告)日：2015-10-01
申请号：US14231200
申请日：2014-03-31
发明人： Shyh-Horng YANG , Chung-Kai LIN , Chung-Hsing WANG , Kuo-Nan YANG , Shou-En LIU , Jhong-Sheng WANG , Tan-Li CHOU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/80
摘要： A method of designing a circuit includes receiving a circuit design, and determining a temperature change of at least on back end of line (BEOL) element of the circuit design. The method further includes identifying at least one isothermal region within the circuit design; and determining, using a processor, a temperature increase of at least one front end of line (FEOL) device within the at least one isothermal region. The method further includes combining the temperature change of the at least one BEOL element with the temperature change of the at least one FEOL device, and comparing the combined temperature change with a threshold value.
摘要翻译： 一种设计电路的方法包括接收电路设计，并确定电路设计的至少后端（BEOL）元件的温度变化。 该方法还包括识别电路设计内的至少一个等温区域; 以及使用处理器确定所述至少一个等温区域内的至少一个前端（FEOL）装置的温度升高。 该方法还包括将至少一个BEOL元件的温度变化与至少一个FEOL装置的温度变化组合，以及将组合的温度变化与阈值进行比较。
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公开(公告)号：US20210342515A1
公开(公告)日：2021-11-04
申请号：US17377635
申请日：2021-07-16
发明人： Hiranmay BISWAS , Kuo-Nan YANG , Chung-Hsing WANG
IPC分类号： G06F30/392 , H01L23/528 , H01L23/50 , H01L23/522 , G06F30/394
摘要： Power grid of an integrated circuit (IC) is provided. A plurality of first power lines are formed in a first metal layer. A plurality of second power lines are formed in the first metal layer and parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. A plurality of third power lines formed in a second metal layer, and the third power lines are perpendicular to the first power lines. A plurality of fourth power lines are formed in the second metal layer and parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. Distances from each of the third power lines to two adjacent fourth power lines are different, and distances from each of the fourth power lines to two adjacent third power lines are the same.
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公开(公告)号：US20210271799A1
公开(公告)日：2021-09-02
申请号：US17325787
申请日：2021-05-20
发明人： John LIN , Chin-Shen LIN , Kuo-Nan YANG , Chung-Hsing WANG
IPC分类号： G06F30/398 , G03F1/82 , G03F1/70 , G03F1/36
摘要： An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a first voltage supply having the first supply voltage.
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