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公开(公告)号：US20230124119A1
公开(公告)日：2023-04-20
申请号：US18066154
申请日：2022-12-14
IPC分类号： H01L27/02 , G06F1/3287
摘要： An integrated circuit includes a gated circuit configured to operate on a first or second voltage, a header circuit, a first power rail and a second power rail on a back-side of a wafer, a third power rail on the back-side of the wafer, and a fourth power rail on a front-side of the wafer. The first and second power rail extend in a first direction, and are separated from each other in a second direction. The third power rail is between the first and second power rail in the second direction. The third power rail is configured to supply the second voltage to the gated circuit. The fourth power rail includes a first set of conductors extending in the second direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit, and is separated from each other in the first direction.
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公开(公告)号：US20230064108A1
公开(公告)日：2023-03-02
申请号：US17446022
申请日：2021-08-26
发明人： Wei-Ling CHANG , Chih-Liang CHEN , Chia-Tien WU , Guo-Huei WU
IPC分类号： H01L23/528 , H01L23/522 , H01L21/8238
摘要： An integrated circuit includes a plurality of horizontal conducting lines in a first connection layer, a plurality of gate-conductors below the first connection layer, a plurality of terminal-conductors below the first connection layer, and a via-connector directly connecting one of the horizontal conducting lines with one of the gate-conductors or with one of the terminal-conductors. The integrated circuit also includes a plurality of vertical conducting lines in a second connection layer above the first connection layer, and a plurality of pin-connectors for a circuit cell. A first pin-connector is directly connected between a first horizontal conducting line and a first vertical conducting line atop one of the gate-conductors. A second pin-connector is directly connected between a second horizontal conducting line and a second vertical conducting line atop a vertical boundary of the circuit cell.
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公开(公告)号：US20230036522A1
公开(公告)日：2023-02-02
申请号：US17390177
申请日：2021-07-30
发明人： Chih-Liang CHEN , Guo-Huei WU , Ching-Wei TSAI , Shang-Wen CHANG , Li-Chun TIEN
IPC分类号： H01L23/528 , H01L27/088 , H01L29/06 , H01L21/8234
摘要： An integrated circuit device includes a first-type active-region semiconductor structure, a first gate-conductor, a second-type active-region semiconductor structure that is stacked with the first-type active-region semiconductor structure, and a second gate-conductor. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device also includes a front-side power rail and a front-side signal line in the front-side conductive layer and includes a back-side power rail and a back-side signal line in the back-side conductive layer. The integrated circuit device also includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail. The integrated circuit device further includes a drain conductive segment connected to either the front-side signal line or the back-side signal line.
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公开(公告)号：US20230035939A1
公开(公告)日：2023-02-02
申请号：US17390108
申请日：2021-07-30
发明人： Wei-Hsin TSAI , Hui-Zhong ZHUANG , Chih-Liang CHEN , Li-Chun TIEN
IPC分类号： H01L27/02 , H01L27/092 , H01L23/522 , H01L21/8238
摘要： A semiconductor device, includes a first metal layer, a second metal layer, and at least one conductive via. The first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction, wherein the second conductor is directly adjacent to the first conductor. The second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. The at least one conductive via connects the first conductor and the second conductor through the third conductor.
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公开(公告)号：US20230009224A1
公开(公告)日：2023-01-12
申请号：US17371631
申请日：2021-07-09
发明人： Jian-Sing LI , Chi-Yu LU , Hui-Zhong ZHUANG , Chih-Liang CHEN
IPC分类号： H01L27/02 , H01L27/092 , H01L29/423 , H01L21/8238 , G06F30/392
摘要： A method of fabricating an integrated circuit. The method includes generating two first-type active zones and two second-type active zones, and generating a gate-strip intersecting the two first-type active zones and the two second-type active zones. The method further includes patterning one or more poly cuts intersecting the gate-strip based on a determination of a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.
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公开(公告)号：US20220367458A1
公开(公告)日：2022-11-17
申请号：US17875148
申请日：2022-07-27
发明人： Kuo-Cheng CHING , Chih-Hao WANG , Chih-Liang CHEN , Shi Ning JU
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/66 , H01L29/06 , H01L29/78 , H01L21/8238
摘要： In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.
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公开(公告)号：US20210343646A1
公开(公告)日：2021-11-04
申请号：US17167646
申请日：2021-02-04
发明人： Chih-Liang CHEN , Li-Chun TIEN
IPC分类号： H01L23/528 , H01L29/06 , H01L29/423 , H01L29/45 , H01L29/786 , H01L21/02 , H01L21/285 , H01L21/306 , H01L29/66
摘要： A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via.
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公开(公告)号：US20230114558A1
公开(公告)日：2023-04-13
申请号：US18065963
申请日：2022-12-14
发明人： Guo-Huei WU , Pochun WANG , Wei-Hsin TSAI , Chih-Liang CHEN , Li-Chun TIEN
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522
摘要： An integrated circuit includes a first power rail, a conductive structure, a first active region of a first set of transistors and a second active region of a second set of transistors. The first power rail is on a back-side of a substrate, extends in a first direction, and is configured to supply a first supply voltage. The first active region extends in the first direction, and is on a first level of a front-side of the substrate opposite from the back-side. The second active region extends in the first direction, is on the first level of the front-side of the substrate, and is separated from the first active region in a second direction different from the first direction. The conductive structure is on the back-side of the substrate, extends in the first direction, and is electrically coupled to the first active region and the second active region.
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公开(公告)号：US20230045167A1
公开(公告)日：2023-02-09
申请号：US17395126
申请日：2021-08-05
发明人： Guo-Huei WU , Shih-Wei PENG , Wei-Cheng LIN , Hui-Zhong ZHUANG , Chih-Liang CHEN , Li-Chun TIEN , Lee-Chung LU
IPC分类号： H01L27/118 , H01L21/8238 , H01L21/768 , H01L27/02 , G06F30/392 , G06F30/31
摘要： An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.
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公开(公告)号：US20230008866A1
公开(公告)日：2023-01-12
申请号：US17466417
申请日：2021-09-03
发明人： Chih-Yu LAI , Chih-Liang CHEN , Chi-Yu LU , Shang-Hsuan CHIU
IPC分类号： H01L23/48 , H01L21/768 , H01L25/065 , H01L27/06 , H01L27/02
摘要： A semiconductor device includes a substrate, a first cell having a first functionality, and a second cell having a second functionality. The first cell includes a first portion on a first side of the substrate, wherein the first portion includes a first conductive element; a second portion on a second side of the substrate, wherein the second portion includes a second conductive element; and a first conductive via extending through the substrate and electrically connecting the first conductive element to the second conductive element. The second cell includes a third portion on the first side of the substrate, wherein the third portion includes a third conductive element; a fourth portion on the second side of the substrate, wherein the fourth portion includes a fourth conductive element; and a second conductive via extending through the substrate and electrically connecting the third conductive element to the fourth conductive element.
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