公开(公告)号：US06487250B1

公开(公告)日：2002-11-26

申请号：US09401325

申请日：1999-09-23

申请人： Tetsuro Kato ,  Seiichi Saito ,  Keitaro Yamagishi

发明人： Tetsuro Kato ,  Seiichi Saito ,  Keitaro Yamagishi

IPC分类号： H04B300

CPC分类号： H04L25/029 ,  H04L25/0278

摘要： When a change of an output signal is detected by an output-signal-state-change detector, a continuous-change performing part controls an output impedance changing part, which is provided between an output buffer and a signal line, so as to continuously change an output impedance from low impedance to high impedance, at the changing timing of the output signal.

摘要翻译： 当输出信号状态变化检测器检测到输出信号的变化时，连续变化执行部分控制输出缓冲器和信号线之间的输出阻抗变化部分，以便连续变化 在输出信号的变化时刻，从低阻抗到高阻抗的输出阻抗。

公开(公告)号：US06477212B1

公开(公告)日：2002-11-05

申请号：US09756382

申请日：2001-01-08

申请人： Thomas J. Bingel ,  Ramon B. Hazen

发明人： Thomas J. Bingel ,  Ramon B. Hazen

IPC分类号： H04B300

CPC分类号： H04L25/085

摘要： The present invention provides a method and apparatus for eliminating or reducing local area and broad area interference in a twisted pair transmission system. The apparatus of the present invention includes a detection device, such as an antenna, for example, for detecting electromagnetic interference coupled into a twisted pair line, a sampling/scaling device which samples and scales the detected signal, and a combiner device which combines a signal correction component with the signal received over the twisted pair by a differential receiver. The sampling/scaling device preferably includes an analog-to-digital converter (ADC) which converts the detected analog signal into a digital signal and a digital signal processor, which receives the digital signal from the ADC and processes the signal to generate a correction signal. The correction signal is then subtracted from the signal received by the differential receiver. The sampling/scaling device may be fixed or adaptive.

摘要翻译： 本发明提供一种用于消除或减少双绞线传输系统中局部区域和广域干扰的方法和装置。 本发明的装置包括例如用于检测耦合到双绞线中的电磁干扰的天线等检测装置，对所检测到的信号进行采样和缩放的采样/缩放装置，以及组合器装置 信号校正分量，通过差分接收机通过双绞线接收的信号。 采样/缩放装置优选地包括将检测到的模拟信号转换成数字信号的数模转换器（ADC）和数字信号处理器，数字信号处理器从ADC接收数字信号并处理信号以产生校正信号 。 然后从由差分接收器接收的信号中减去校正信号。 采样/缩放装置可以是固定的或适应的。

公开(公告)号：US06466627B1

公开(公告)日：2002-10-15

申请号：US09245810

申请日：1999-02-05

申请人： Isamu Kuwana

发明人： Isamu Kuwana

IPC分类号： H04B300

CPC分类号： H04L25/0286 ,  H04L25/0266 ,  Y10T307/713 ,  Y10T307/735 ,  Y10T307/839 ,  Y10T307/852 ,  Y10T307/931

摘要： A pulse signal transmitting circuit generates a pulse signal having an enhanced high-frequency component with a reduced power loss. A pulse signal is transmitted to a load circuit through a transmission cable connected to a secondary winding of a transformer. First and second transistors are connected to a primary winding of the transformer. A voltage output from an external power source is input to the primary winding of the transformer when at least one of the first and second transistors is conductive so that a pulse voltage signal is input to the transformer. A booster power supply circuit is located between the external power source and a middle point of the primary winding of the transformer. The booster power supply circuit superimposes a boost voltage onto the voltage input to the primary winding of the transformer so that a high-frequency component of the pulse voltage signal input to the primary winding of the transformer is enhanced.

摘要翻译： 脉冲信号发送电路产生具有降低的功率损耗的具有增强的高频分量的脉冲信号。 脉冲信号通过连接到变压器的次级绕组的传输电缆传输到负载电路。 第一和第二晶体管连接到变压器的初级绕组。 当第一和第二晶体管中的至少一个导通时，来自外部电源的电压输出被输入到变压器的初级绕组，使得脉冲电压信号被输入到变压器。 升压电源电路位于外部电源和变压器初级绕组的中点之间。 升压电源电路将升压电压叠加在输入到变压器的初级绕组的电压上，使得输入到变压器的初级绕组的脉冲电压信号的高频分量得到增强。

公开(公告)号：US06393062B1

公开(公告)日：2002-05-21

申请号：US09264803

申请日：1999-03-09

申请人： Bruce M. Furman ,  Charles M. Allen

发明人： Bruce M. Furman ,  Charles M. Allen

IPC分类号： H04B300

CPC分类号： H04L25/03885

摘要： The present invention overcomes ISI by precompensating for the anticipated high-frequency energy losses in the transmission media. This precompensation is accomplished using a preemphasis waveform, i.e., driving the differential signal to a value larger than normal on a signal edge. Preemphasis increases the slew rate of edges inside data with a lot of transitions relative to data with fewer transitions, thereby compensating for the low-pass effects of the transmission cable. The present invention further contemplates adaptive control for ensuring that varying operating conditions do not effect preemphasis waveform generation. The first approach involves tracking the operation of a replicate driver for each main driver and adaptively controlling each main driver depending upon feedback from the replicate driver. A second approach, that is both more complicated and more effective, involves measuring the signal and the line impedance at the output of the main driver and adaptively controlling the main driver in response.

摘要翻译： 本发明通过对传输介质中预期的高频能量损耗进行预补偿来克服ISI。 该预补偿使用预加重波形完成，即，将信号边沿上的差分信号驱动到比正常大的值。 预加重增加数据中边缘的转换速率，相对于具有较少转换的数据具有大量转换，从而补偿传输电缆的低通效应。 本发明进一步考虑了自适应控制，以确保变化的操作条件不影响预加重波形生成。 第一种方法包括跟踪每个主驱动器的复制驱动程序的操作，并根据来自复制驱动程序的反馈自适应地控制每个主驱动程序。 第二种方法更复杂，更有效，包括测量主驱动器输出端的信号和线路阻抗，并自适应地控制主驱动器。

公开(公告)号：US06381283B1

公开(公告)日：2002-04-30

申请号：US09168225

申请日：1998-10-07

申请人： Vinod K. Bhardwaj ,  Larry W. Haugen

发明人： Vinod K. Bhardwaj ,  Larry W. Haugen

IPC分类号： H04B300

CPC分类号： H01R24/64 ,  H01R13/6658 ,  H05K7/1092

摘要： An integrated module incorporates not only a cable socket, but also a chip carrier for an integrated circuit and a daughter card for discrete components. The module can be mounted on any printed circuit board, within a switch, router, hub or other network device. A network socket, one or more integrated circuits and all discrete components (resistors, capacitors, coil, etc.) are contained within the module. The functionality of a transceiver and a media access controller are split into a digital portion and an analog portion. Each of the digital and analog functionality is implemented on a separate integrated circuit and both integrated circuits are placed next to one another in the chip carrier within the integrated module. Shielding around the socket is extended to surround the entire integrated module. The metal shielding extends underneath the integrated module and contacts the copper base of the chip carrier to serve as a heat sink. Any number of integrated modules are ganged together and a single electromagnetic shield placed around all of the integrated modules. A light pipe is used in conjunction with the socket instead of traditional light-emitting diodes. A chip carrier by itself has pins bent both downward to interface to a particular device such as computer board, network switch, hub, router, etc., and pins bent upward to attach to an above daughter card. A chip carrier also contains one or more integrated circuits and a daughter card mounted on top of the chip carrier.

摘要翻译： 集成模块不仅包括电缆插座，还包括用于集成电路的芯片载体和用于分立组件的子卡。 该模块可以安装在任何印刷电路板，交换机，路由器，集线器或其他网络设备内。 网络插座，一个或多个集成电路和所有分立元件（电阻，电容器，线圈等）都包含在模块内。 收发机和媒体接入控制器的功能被分为数字部分和模拟部分。 数字和模拟功能中的每一个在单独的集成电路上实现，并且两个集成电路彼此相邻放置在集成模块内的芯片载体中。 扩展插槽周围的屏蔽可以围绕整个集成模块。 金属屏蔽层延伸在集成模块的下方，并与芯片载体的铜基接触，用作散热器。 任何数量的集成模块组合在一起，并将一个电磁屏蔽放置在所有集成模块的周围。 光管与插座配合使用，而不是传统的发光二极管。 芯片载体本身具有向下弯曲以与诸如计算机板，网络交换机，集线器，路由器等的特定设备接口的引脚，并且引脚向上弯曲以附接到上述子卡。 芯片载体还包含一个或多个集成电路和安装在芯片载体顶部上的子卡。

公开(公告)号：US06370200B1

公开(公告)日：2002-04-09

申请号：US09127893

申请日：1998-08-03

申请人： Satoshi Takahashi

发明人： Satoshi Takahashi

IPC分类号： H04B300

CPC分类号： H04L25/14 ,  H04L7/0041 ,  H04L7/02

摘要： In simultaneous transmission of a signal using plural transmission lines, a synchronous cycle is set, plural signals A, B, C and D are simultaneously transmitted to the plural transmission lines, and the plural signals A through D transmitted through the plural transmission lines are received. Delay times &tgr;A, &tgr;B, &tgr;C and &tgr;D of the plural signals received in the synchronous cycle are detected, and the delay times of the transmission lines are adjusted on the basis of these detected delay times so that the simultaneously output signals A through D can be simultaneously received after passing through the plural transmission lines. Accordingly, even when a delay time between signals is long with a phase shift exceeding one cycle of a clock signal, the phase shift between the signals can be adjusted to be within one cycle.

摘要翻译： 在使用多条传输线同时传输信号的同时，设置多个信号A，B，C和D，并将多个信号A，B，C和D同时发送到多个传输线，并且通过多个传输线传输的多个信号A至D被接收 。 检测在同步周期中接收到的多个信号的延迟时间＆amp; A，＆amp; T，C和T，并且基于这些检测到的延迟时间来调整传输线的延迟时间， 同时输出信号A至D可以在通过多条传输线之后同时接收。 因此，即使当信号之间的延迟时间长于超过时钟信号的一个周期的相移时，也可以将信号之间的相移调整到一个周期内。

公开(公告)号：US06332004B1

公开(公告)日：2001-12-18

申请号：US09429892

申请日：1999-10-29

申请人： Kevin T. Chan

发明人： Kevin T. Chan

IPC分类号： H04B300

CPC分类号： H04L25/08 ,  H04B3/23 ,  H04B3/32 ,  H04L12/10 ,  H04L25/0276 ,  H04L25/0282 ,  H04L25/0286 ,  H04L25/03834 ,  H04L25/14

摘要： A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). A discrete-time analog filter is integrated with the DAC line driver to provide additional EMI emissions suppression. A multiplicity of output cells produce an output signal that is responsive to a plurality of digitized input data samples. A timing circuit generates timing signals for dividing each digitized input data sample into a first time segment and a second time segment. A control logic connected to each output cell generates control signals to drive each output cell to produce a portion of the output signal for the first time segment and the full output signal for the second time segment.

摘要翻译： 用于非屏蔽双绞线（UTP）数据通信应用的功率高效和降低的电磁干扰（EMI）发射器。 发送数据由数/模转换器（DAC）转换为电流模式模拟波形。 离散时间模拟滤波器与DAC线路驱动器集成，以提供额外的EMI发射抑制。 多个输出单元产生响应多个数字化输入数据样本的输出信号。 定时电路产生用于将每个数字化的输入数据样本分成第一时间段和第二时间段的定时信号。 连接到每个输出单元的控制逻辑产生控制信号以驱动每个输出单元以产生第一时间段的输出信号的一部分和第二时间段的全输出信号。

公开(公告)号：US06301305B1

公开(公告)日：2001-10-09

申请号：US09089393

申请日：1998-06-03

申请人： Katsuhiro Ohuchi ,  Morio Sato

发明人： Katsuhiro Ohuchi ,  Morio Sato

IPC分类号： H04B300

CPC分类号： H04L25/029

摘要： A transmitting apparatus of simple circuit configuration is provided as having turn off time (cut off delay time) of an output transistor shortened. The potential of a low-level signal is inputted to an input terminal of a first transistor through a resistor. The potential of a high-level signal is inputted to an input terminal of a second transistor through a resistor. A control circuit is connected to the input terminals of the first and second transistors and when a high-level signal is to be transmitted to the communication line, the control circuit enters a high-impedance state with respect to the input terminal of the first transistor and outputs a low-level signal to the input terminal of the second transistor. When a low-level signal is to be transmitted over the communication line, the control circuit outputs a high-level signal to the input terminal of the first transistor and develops a high-impedance state with respect to the input terminal of the second transistor.

摘要翻译： 具有简单电路结构的发送装置被提供为具有缩短的输出晶体管的截止时间（截止延迟时间）。 低电平信号的电位通过电阻器输入到第一晶体管的输入端。 高电平信号的电位通过电阻器输入到第二晶体管的输入端。 控制电路连接到第一和第二晶体管的输入端，并且当高电平信号要发送到通信线路时，控制电路相对于第一晶体管的输入端子进入高阻抗状态 并将低电平信号输出到第二晶体管的输入端。 当通过通信线路发送低电平信号时，控制电路向第一晶体管的输入端输出高电平信号，并相对于第二晶体管的输入端产生高阻抗状态。

公开(公告)号：US06285718B1

公开(公告)日：2001-09-04

申请号：US09500681

申请日：2000-02-09

申请人： Ilan Reuven

发明人： Ilan Reuven

IPC分类号： H04B300

CPC分类号： H04L25/4921 ,  H04L27/00

摘要： This invention discloses an apparatus for transmission of high speed data over communication channels, the apparatus including a modulator operative to modulate an outgoing stream of digital data, thereby to generate an outgoing signal, and a demodulator operative to demodulate an incoming signal, thereby to generate an incoming stream of digital data, wherein the modulator comprises a band suppressor for suppressing portions of the outgoing signal which have specified frequencies.

摘要翻译： 本发明公开了一种用于通过通信信道传输高速数据的装置，该装置包括一个调制器，用于调制数字数据的输出流，从而产生输出信号，以及解调器，用于解调输入信号，从而产生 输入数字数据流，其中调制器包括用于抑制具有指定频率的输出信号的部分的频带抑制器。

公开(公告)号：US06278740B1

公开(公告)日：2001-08-21

申请号：US09197324

申请日：1998-11-19

申请人： Keith D. Nordyke

发明人： Keith D. Nordyke

IPC分类号： H04B300

CPC分类号： H04B3/00 ,  H04L5/20

摘要： Differential signaling between integrated circuit chips uses fewer than 2 external wires per bit transmitted. Rather than pairing wires into groups of two, the external wires are part of a larger group of 2i+2 wires. Half of the wires in the group are driven low while the other half of the wires are driven high. Since the wires are not paired, adjacent wires can have the same logical state. Differential comparators in the receiver chip compare each wire with all other wires in the group. All outputs of comparators that have a wire as one of its two inputs are input to a majority logic block that evaluates the logical state of the wire. Since half of the wires are in one state, the majority of the remaining wires are in the opposite state of the wire being evaluated. Thus the majority of the comparator outputs indicate the opposite state of the wire being evaluated. Each of the external wires is evaluated by differential comparators and majority logic to get the logical states of each of the external wires. Codes having equal numbers of high and low wires are used to encode binary data over the external wires. Eight external wires can encode a 6-bit binary value, which is 1.5 wires per bit using the (2i+2)-wire codes.

摘要翻译： 集成电路芯片之间的差分信号每位传输使用少于2个外部线。 不是将电线配对成两组，外部电线是2i + 2线较大组的一部分。 组中的一半电线被驱动为低电平，而另一半电线被驱动为高电平。 由于线不配对，相邻线可具有相同的逻辑状态。 接收芯片中的差分比较器将每根导线与组中所有其他导线进行比较。 具有作为其两个输入之一的导线的比较器的所有输出被输入到评估导线的逻辑状态的多数逻辑块。 由于一半的电线处于一个状态，所以剩余电线的大部分处于被评估的电线的相反状态。 因此，大多数比较器输出表示正在评估的电线的相反状态。 每个外部电线由差分比较器和多数逻辑来评估，以获得每个外部电线的逻辑状态。 具有相等数量的高和低导线的代码用于通过外部线编码二进制数据。 八个外部线可以使用（2i + 2） - 线代码对6位二进制值进行编码，每位为1.5线。