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公开(公告)号：US10014867B1
公开(公告)日：2018-07-03
申请号：US15391970
申请日：2016-12-28
Applicant: AUCMOS Technologies USA, Inc.
Inventor： Teh-Shang Lu
Abstract: A phase-locked loop circuit includes (a) a phase frequency detector which receives the input signal of the phase-locked loop and a feedback signal that is derived from the output signal of the phase-locked loop, the phase-frequency detector providing a phase-difference signal indicating a difference in phase or frequency between the input signal and the feedback signal; (b) a voltage control oscillator which receives a voltage control signal and which provide the output signal of the phase-locked loop according to the voltage control signal; (c) first and second charge pump-filter circuits each receiving the phase difference signal and each comprising: (i) a charge pump circuit which provide a predetermined signal in accordance with the phase difference signal; and (ii) a filter circuit receiving the predetermined signal to provide a filtered signal, the filter circuit comprising one or more resistors and one or more capacitors; and (d) a summing circuit which sums the filtered signal of the first charge pump-filter circuit and the filtered signal of the second charge pump-filter circuit to provide the voltage control signal.
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公开(公告)号：US09972374B1
公开(公告)日：2018-05-15
申请号：US15391991
申请日：2016-12-28
Applicant: AUCMOS Technologies USA, Inc.
Inventor： Tianhong Yan
IPC: G11C11/22
CPC classification number: G11C11/2273 , G11C11/2253 , G11C11/2255 , G11C11/2257 , G11C11/2259 , G11C11/2275 , G11C2207/002
Abstract: A ferroelectric random access memory (FeRAM) array includes (a) a first section of FeRAM cells sharing a first plate line and a word line; and (b) a second section of FeRAM cells sharing a second plate line and the word line, wherein the first plate line and the second plate line are electrically unconnected, and wherein only the first section of FeRAM cells or the second section of FeRAM cells, but not both, are selected for a read operation at any given time. In each section of the FeRAM cells, a plate line selection cell connects the corresponding plate line to a plate line selection line. Each FeRAM cell in each section is read or written over a pair of bit lines running in a direction transverse to the word line of the section, and the plate line selection line runs along a direction parallel to the bit lines.
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公开(公告)号：US10803918B2
公开(公告)日：2020-10-13
申请号：US15984187
申请日：2018-05-18
Applicant: AUCMOS Technologies USA, Inc.
Inventor： Adrian E. Ong
IPC: G11C11/22 , H01L27/11507 , H01L23/528 , H01L27/092
Abstract: A plate line segment selector circuit, coupled to a plate line segment, a plate line and a word line, may include (a) a P-channel transistor having a gate terminal connected to the plate line, a source terminal connected to the word line, and a drain terminal connected to the plate line segment; and (b) a N-channel transistor having a gate terminal connected to the plate line, a drain terminal connected to the plate line, and a source terminal connected to a ground reference voltage source. Alternatively, the plate line segment selector circuit may include: (a) a P-channel transistor having a gate terminal connected to the plate line, a source terminal connected to a predetermined voltage source, and a drain terminal; (b) a N-channel transistor having a gate terminal connected to the plate line, a source terminal connected to a ground reference voltage source, and a drain terminal; and (c) a field effect transistor having a gate terminal connected to the word line, a first drain or source terminal connected to the drain terminals of the P-channel and N-channel transistors and a second drain or source terminal connected to the plate line segment.
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公开(公告)号：US20190392884A1
公开(公告)日：2019-12-26
申请号：US16019328
申请日：2018-06-26
Applicant: AUCMOS Technologies USA, Inc.
Inventor： Adrian Ong
Abstract: A ferroelectric memory array includes (a) a driver circuit providing a first signal and a second signal; (b) word lines each providing a word line signal; and (c) memory array sections. Each memory array section may include: (a) bit lines; (b) plate line segments each associated with a corresponding one of the word line signals; (c) local plate line decoders, each local plate line decoder (i) being associated with one of the plate line segments, (ii) receiving the corresponding word line signal of the associated plate line segment, the first signal and the second signal, and (iii) providing predetermined voltages on the associated plate line segment according to the received word line signal, the first signal and the second signal; and (d) memory cells, each memory cells having one or more ferroelectric capacitor connected between one of the plate line segments and one of the bit lines. The predetermined voltages output from a local plate decoder may include a voltage of the word line signal, a power supply voltage, or one half the power supply voltage.
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公开(公告)号：US10818334B2
公开(公告)日：2020-10-27
申请号：US16019328
申请日：2018-06-26
Applicant: AUCMOS Technologies USA, Inc.
Inventor： Adrian Ong
Abstract: A ferroelectric memory array includes (a) a driver circuit providing a first signal and a second signal; (b) word lines each providing a word line signal; and (c) memory array sections. Each memory array section may include: (a) bit lines; (b) plate line segments each associated with a corresponding one of the word line signals; (c) local plate line decoders, each local plate line decoder (i) being associated with one of the plate line segments, (ii) receiving the corresponding word line signal of the associated plate line segment, the first signal and the second signal, and (iii) providing predetermined voltages on the associated plate line segment according to the received word line signal, the first signal and the second signal; and (d) memory cells, each memory cells having one or more ferroelectric capacitor connected between one of the plate line segments and one of the bit lines. The predetermined voltages output from a local plate decoder may include a voltage of the word line signal, a power supply voltage, or one half the power supply voltage.
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Patent Agency Ranking
公开(公告)号：US09812204B1
公开(公告)日：2017-11-07
申请号：US15391982
申请日：2016-12-28
Applicant: AUCMOS Technologies USA, Inc.
Inventor： Tianhong Yan , Yung-Tin Chen
IPC: G11C11/00 , G11C14/00 , H01L27/11 , H01L27/11502
CPC classification number: G11C14/0072 , G11C11/2275 , H01L27/11 , H01L27/1104 , H01L27/11502 , H01L27/11507
Abstract: A ferroelectric static random access memory (FeSRAM) cell includes (a) first and second cross-coupled inverters connected between a power supply voltage signal and a ground reference voltage signal and holding a data signal represented in a complementary manner in first and second common data terminals; (b) first and second select transistors coupled respectively to the first and second common data terminals of the cross-coupled inverters; and (c) first, second, third and fourth ferroelectric capacitors, wherein the first and second ferroelectric capacitors couple the first common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively, and wherein the third and the fourth ferroelectric capacitors couple the second common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively.
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公开(公告)号：US20190355404A1
公开(公告)日：2019-11-21
申请号：US15984187
申请日：2018-05-18
Applicant: AUCMOS Technologies USA, Inc.
Inventor： Adrian E. Ong
IPC: G11C11/22 , H01L27/11507 , H01L27/092 , H01L23/528
Abstract: A plate line segment selector circuit, coupled to a plate line segment, a plate line and a word line, may include (a) a P-channel transistor having a gate terminal connected to the plate line, a source terminal connected to the word line, and a drain terminal connected to the plate line segment; and (b) a N-channel transistor having a gate terminal connected to the plate line, a drain terminal connected to the plate line, and a source terminal connected to a ground reference voltage source. Alternatively, the plate line segment selector circuit may include: (a) a P-channel transistor having a gate terminal connected to the plate line, a source terminal connected to a predetermined voltage source, and a drain terminal; (b) a N-channel transistor having a gate terminal connected to the plate line, a source terminal connected to a ground reference voltage source, and a drain terminal; and (c) a field effect transistor having a gate terminal connected to the word line, a first drain or source terminal connected to the drain terminals of the P-channel and N-channel transistors and a second drain or source terminal connected to the plate line segment.
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公开(公告)号：US10283183B2
公开(公告)日：2019-05-07
申请号：US15391996
申请日：2016-12-28
Applicant: AUCMOS Technologies USA, Inc.
Inventor： Tianhong Yan
IPC: G11C11/22
Abstract: A method for programming a memory cell to a predetermined programmed state includesL (a) preparing the memory cell for a write operation; (b) sending a train of programming pulses, each programming pulse being a pulse having a magnitude sufficient to program the memory cell to the predetermined programmed state; (c) preparing the memory cell for a read operation; and (d) reading the programmed state of the memory cell to ascertain whether or not the predetermined programmed state is in the memory cell. In one embodiment, the method repeats steps (a)-(d), when the programmed state of the memory cell is not the predetermined programmed state. In one embodiment, the number of times steps (a)-(d) is repeated is determined based on both a probability of successfully writing the memory cell using a single write pulse and a probability of chaotic switching.
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公开(公告)号：US09971373B1
公开(公告)日：2018-05-15
申请号：US15391966
申请日：2016-12-28
Applicant: AUCMOS Technologies USA, Inc.
Inventor： Teh-Shang Lu
CPC classification number: G05F3/24 , H03H7/0138
Abstract: A reference voltage generation circuit includes (a) a native MOS transistor coupled to between a power supply voltage source, and the output terminal of the reference voltage generation circuit; (b) an enhancement mode MOS transistor coupled between the output terminal and ground; and (c) a filter circuit that are coupled to the gate terminals of both the native MOS transistor, the enhancement mode transistor and the output terminal of the reference voltage generation circuit, in which the filter circuit has a transfer function including one or more zeroes at predetermined noise frequencies.
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公开(公告)号：US09899085B1
公开(公告)日：2018-02-20
申请号：US15393585
申请日：2016-12-29
Applicant: AUCMOS Technologies USA, Inc.
Inventor： Tianhong Yan
CPC classification number: G11C14/0072 , G11C11/22 , G11C11/221
Abstract: A FeSRAM cell includes (a) first and second inverters between a power supply voltage and a ground reference cross-coupled to each other, the first and second cross-coupled inverters providing first and second data terminals; (b) first and second select transistors respectively coupled to the first and second data terminals to control access to the first second data terminals; and (c) first and second ferroelectric capacitors coupled between a first plate line and respectively the first and second data terminals, the first plate line receiving a negative programming voltage having a magnitude greater than the power supply voltage to allow programming one of the first and second ferroelectric capacitors into a first non-volatile programmed state.
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