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公开(公告)号：US09972374B1
公开(公告)日：2018-05-15
申请号：US15391991
申请日：2016-12-28
发明人： Tianhong Yan
IPC分类号： G11C11/22
CPC分类号： G11C11/2273 , G11C11/2253 , G11C11/2255 , G11C11/2257 , G11C11/2259 , G11C11/2275 , G11C2207/002
摘要： A ferroelectric random access memory (FeRAM) array includes (a) a first section of FeRAM cells sharing a first plate line and a word line; and (b) a second section of FeRAM cells sharing a second plate line and the word line, wherein the first plate line and the second plate line are electrically unconnected, and wherein only the first section of FeRAM cells or the second section of FeRAM cells, but not both, are selected for a read operation at any given time. In each section of the FeRAM cells, a plate line selection cell connects the corresponding plate line to a plate line selection line. Each FeRAM cell in each section is read or written over a pair of bit lines running in a direction transverse to the word line of the section, and the plate line selection line runs along a direction parallel to the bit lines.
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公开(公告)号：US09812204B1
公开(公告)日：2017-11-07
申请号：US15391982
申请日：2016-12-28
发明人： Tianhong Yan , Yung-Tin Chen
IPC分类号： G11C11/00 , G11C14/00 , H01L27/11 , H01L27/11502
CPC分类号： G11C14/0072 , G11C11/2275 , H01L27/11 , H01L27/1104 , H01L27/11502 , H01L27/11507
摘要： A ferroelectric static random access memory (FeSRAM) cell includes (a) first and second cross-coupled inverters connected between a power supply voltage signal and a ground reference voltage signal and holding a data signal represented in a complementary manner in first and second common data terminals; (b) first and second select transistors coupled respectively to the first and second common data terminals of the cross-coupled inverters; and (c) first, second, third and fourth ferroelectric capacitors, wherein the first and second ferroelectric capacitors couple the first common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively, and wherein the third and the fourth ferroelectric capacitors couple the second common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively.
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公开(公告)号：US20180122451A1
公开(公告)日：2018-05-03
申请号：US15391991
申请日：2016-12-28
发明人： Tianhong Yan
IPC分类号： G11C11/22
CPC分类号： G11C11/2273 , G11C11/2253 , G11C11/2255 , G11C11/2257 , G11C11/2259 , G11C11/2275 , G11C2207/002
摘要： A ferroelectric random access memory (FeRAM) array includes (a) a first section of FeRAM cells sharing a first plate line and a word line; and (b) a second section of FeRAM cells sharing a second plate line and the word line, wherein the first plate line and the second plate line are electrically unconnected, and wherein only the first section of FeRAM cells or the second section of FeRAM cells, but not both, are selected for a read operation at any given time. In each section of the FeRAM cells, a plate line selection cell connects the corresponding plate line to a plate line selection line. Each FeRAM cell in each section is read or written over a pair of bit lines running in a direction transverse to the word line of the section, and the plate line selection line runs along a direction parallel to the bit lines.
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公开(公告)号：US20180122453A1
公开(公告)日：2018-05-03
申请号：US15391996
申请日：2016-12-28
发明人： Tianhong Yan
IPC分类号： G11C11/22
CPC分类号： G11C11/2275 , G11C11/2273 , G11C11/2277
摘要： A method for programming a memory cell to a predetermined programmed state includesL (a) preparing the memory cell for a write operation; (b) sending a train of programming pulses, each programming pulse being a pulse having a magnitude sufficient to program the memory cell to the predetermined programmed state; (c) preparing the memory cell for a read operation; and (d) reading the programmed state of the memory cell to ascertain whether or not the predetermined programmed state is in the memory cell. In one embodiment, the method repeats steps (a)-(d), when the programmed state of the memory cell is not the predetermined programmed state. In one embodiment, the number of times steps (a)-(d) is repeated is determined based on both a probability of successfully writing the memory cell using a single write pulse and a probability of chaotic switching.
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公开(公告)号：US10283183B2
公开(公告)日：2019-05-07
申请号：US15391996
申请日：2016-12-28
发明人： Tianhong Yan
IPC分类号： G11C11/22
摘要： A method for programming a memory cell to a predetermined programmed state includesL (a) preparing the memory cell for a write operation; (b) sending a train of programming pulses, each programming pulse being a pulse having a magnitude sufficient to program the memory cell to the predetermined programmed state; (c) preparing the memory cell for a read operation; and (d) reading the programmed state of the memory cell to ascertain whether or not the predetermined programmed state is in the memory cell. In one embodiment, the method repeats steps (a)-(d), when the programmed state of the memory cell is not the predetermined programmed state. In one embodiment, the number of times steps (a)-(d) is repeated is determined based on both a probability of successfully writing the memory cell using a single write pulse and a probability of chaotic switching.
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公开(公告)号：US09899085B1
公开(公告)日：2018-02-20
申请号：US15393585
申请日：2016-12-29
发明人： Tianhong Yan
CPC分类号： G11C14/0072 , G11C11/22 , G11C11/221
摘要： A FeSRAM cell includes (a) first and second inverters between a power supply voltage and a ground reference cross-coupled to each other, the first and second cross-coupled inverters providing first and second data terminals; (b) first and second select transistors respectively coupled to the first and second data terminals to control access to the first second data terminals; and (c) first and second ferroelectric capacitors coupled between a first plate line and respectively the first and second data terminals, the first plate line receiving a negative programming voltage having a magnitude greater than the power supply voltage to allow programming one of the first and second ferroelectric capacitors into a first non-volatile programmed state.
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