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1.发明授权公开(公告)号：US11265020B2
公开(公告)日：2022-03-01
申请号：US17240080
申请日：2021-04-26
申请人： AccelerComm Limited
摘要： An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=┌n/w┐) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=┌n/w┐) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=┌n/w┐ clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n−k bits adopt a complementary binary value.
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公开(公告)号：US20200220559A1
公开(公告)日：2020-07-09
申请号：US16622894
申请日：2018-06-12
申请人： Robert Maunder , Matthew Brejza , Shida Zhong , Isaac ANDRADE , Taihai Chen
发明人： Robert Maunder , Matthew Brejza , Shida Zhong , Isaac ANDRADE , Taihai Chen
摘要： A polar encoder kernel, a communication unit, an integrated circuit and a method of polar encoding are described. The polar encoder kernal is configured to receive one or more bits from a kernal information block having a kernal block size of N; and output one or more bits from a kernal encoded block having a block size that matches the kernal block size N; wherein the polar encoder kernal comprises a decomposition of a polar code graph having multiple columns that are processed by a reused single datapath, at least one of said multiple columns contains two or more stages and where each column of the multiple columns is further decomposed into one or more polar code sub-graphs and is configured to process encoded bits one polar code sub-graph at a time.
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公开(公告)号：US10439645B2
公开(公告)日：2019-10-08
申请号：US15503379
申请日：2015-07-30
申请人： Accelercomm Limited
发明人： Robert Maunder , An Li , Isaac Perez-Andrade
IPC分类号： H03M13/29 , H03M13/15 , H03M13/00 , H03M13/27 , H03M13/11 , H03M13/37 , H03M13/45 , H04L1/00
摘要： A circuit performs a turbo detection process recovering data symbols from a received signal effected, during transmission, by a Markov process with effect that the data symbols are dependent on preceding data symbols represented as a trellis having a plurality of trellis stages. The circuit comprises processing elements, associated with trellis stages representing these dependencies and each configured to receive soft decision values corresponding to associated data symbols Each processing element configured, in one clock cycle to receive data representing a priori forward and backward state metrics, and a priori soft decision values for data symbols detected for the trellis stage. For each clock cycle of the turbo detection process, the circuit processes, for processing elements representing the trellis stages, the a priori information for associated data symbols detected for the trellis stage, and to provide extrinsic soft decision values corresponding to data symbols for a next clock cycle.
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公开(公告)号：US11962326B2
公开(公告)日：2024-04-16
申请号：US17925589
申请日：2021-05-14
申请人： AccelerComm Limited
发明人： Robert Maunder , Matthew Brejza , Peter Hailes
CPC分类号： H03M13/116 , H03M13/1137 , H03M13/118 , H03M13/616 , H03M13/6561
摘要： An electronic device, configured to perform a series of low-density parity check, LDPC, decoding operations for a parity check matrix, PCM, derived from at least one basegraph having a plurality of rows, includes: two or more check node, CN, sub-processors having input-output (I-O) port(s); and a controller configured to activate a subset of the I-O port(s) based on a current LDPC decoding sub-step of the LDPC decoding operations and the basegraph. The CN sub-processors support: a first single LDPC decoding operation to perform LDPC decoding computations for two or more rows of the PCM that are derived from different orthogonal rows of the plurality of rows in the basegraph; and a second mode whereby two or more of CN sub-processors co-operate to perform LDPC decoding computations for two or more rows of the PCM that are derived from a single row in the basegraph.
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公开(公告)号：US11184109B2
公开(公告)日：2021-11-23
申请号：US16475640
申请日：2018-02-06
申请人： ACCELERCOMM LIMITED
发明人： Robert Maunder , Matthew Brejza , Luping Xiang
摘要： A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbols of the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded data between the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively, during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to provide the a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuit an arbitrarily parallel turbo decoder.
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公开(公告)号：US11043972B2
公开(公告)日：2021-06-22
申请号：US16628825
申请日：2018-07-04
申请人： Accelercomm Limited , Robert Maunder , Matthew Brejza , Shida Zhong , Isaac Perez-Andrade , Taihai Chen
摘要： An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=┌n/w▴) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=┌n/w▴) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=┌n/w▴ clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n−k bits adopt a complementary binary value.
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公开(公告)号：US20210176006A1
公开(公告)日：2021-06-10
申请号：US16475640
申请日：2018-02-06
申请人： ACCELERCOMM LIMITED
发明人： Robert Maunder , Matthew Brejza , Luping Xiang
摘要： A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbols of the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded data between the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively, during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to provide the a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuit an arbitrarily parallel turbo decoder.
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公开(公告)号：US12088320B2
公开(公告)日：2024-09-10
申请号：US17925587
申请日：2021-05-14
申请人： AccelerComm Limited
发明人： Robert Maunder , Matthew Brejza , Peter Hailes
CPC分类号： H03M13/1137 , H03M13/1111 , H04L1/0057
摘要： An electronic device is described that is configured to perform a series of low density parity check, LDPC, decoding operations that use at least one basegraph that comprises two or more columns, each column associated with a set of two or more soft bit values. The electronic device includes two or more rotators, each rotator configured to rotate an order of a subset of two or more soft bit values of the set of two or more soft bit values of a column when activated in an LDPC decoding operation; and wherein rotations associated with each column in each basegraph are performed by a particular one of the rotators of the two or more rotators, wherein each rotator performs rotations for a set of one or more columns, with at least one of the rotators performing rotations for two or more columns in a same basegraph.
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公开(公告)号：US11677419B2
公开(公告)日：2023-06-13
申请号：US17623441
申请日：2020-06-30
申请人： Accelercomm Limited
发明人： Robert Maunder , Matthew Brejza
CPC分类号： H03M13/091 , H03M13/617 , H03M13/098 , H03M13/1168 , H03M13/1575
摘要： A cyclic redundancy check, CRC, decoder circuit having a K-bit input bit sequence, s, comprising information bits and CRC bits; and at least one processor (P) configured to perform a CRC decode computation and configured to: use an inverse of a predefined CRC generator polynomial that encoded the K-bit input bit sequence, s, to produce a data set; compute a CRC syndrome from the data set; and determine whether the CRC syndrome contains any one-valued bits indicative of a CRC error. An LUT stores one or more rows of a CRC generator matrix (G) generated from the inverse of the predefined CRC generator polynomial. A set of mod(−K,P) zero-valued filler bits are appended to an end of the K-bit input bit sequence, wherein an order of the rows in the CRC generator matrix (G) is reversed and aligned with the input bits of the input stream.
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公开(公告)号：US20230344685A1
公开(公告)日：2023-10-26
申请号：US18015509
申请日：2021-07-09
申请人： AccelerComm Limited
发明人： Robert G. Maunder , Aryan Tavakkoli
IPC分类号： H04L25/06 , H03M13/00 , H03M13/29 , H04B1/707 , H04L27/227
CPC分类号： H04L25/067 , H03M13/6325 , H03M13/2957 , H04B1/707 , H04L27/2278
摘要： A communication unit for performing soft-decision demodulation comprises a receiver that receives a transmitted signal having a first set of bits comprising k bits, selected from a set of 2k possible signals according to values of the k bits, and a second set of bits comprising Qm bits based on a phase rotation of the transmitted signal selected from a set of 2Qm possible rotations. The receiver comprises: a demodulator comprising a bank of 2k correlators and is configured to: detect a transmission of each possible transmitted signal, and output 2k phases of the correlator outputs as a third set of inputs. A de-mapper circuit receives the third set of inputs: determines statistics derived from a number of aggregated correlator output phase distributions of the third set of inputs; and calculates and outputs a second set of aposteriori soft bits comprising Qm soft bits.
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